International Business Machines Corporation

Airbnb, Inc.

Michael James Rohn

Timothy Clyde Buchholtz

Daniel Ramirez

Morgan D Davis

Nghia Van Phan

Todd Alan Christensen

Gregory John Uhlmann

Anthony Gus Aipperspach

David Michael Friend

Salvatore Nicholas Storino

Thomas Charles Brennan

Binta Minesh Patel

Bryan Joe Talik

Authentication includes receiving an indication of physical possession of a payment card by a merchant and receiving a purchase request for an authorization of an exchange from the payment account of the cardholder to the merchant. Authentication includes assigning a randomized transaction identifier to the request for the authorization of the exchange. The method also includes transmitting the request for the authorization of the exchange from the payment account of the cardholder to the merchant and receiving the assigned randomized transaction identifier and a randomized authentication identifier associated with the randomized transaction identifier from a payment association, the payment association determining whether the request for the authorization of the exchange is valid. Authentication includes transmitting a copy of the randomized authentication identifier to the mobile device and receiving validation that the transmitted copy of the randomized authentication identifier from the mobile device matches the randomized authentication identifier.

Multi-point authentication for payment transactions

Authentication for payment transaction includes receiving, by a point-of-sale (POS) terminal, an indication that a payment account of a cardholder is associated with a mobile device and receiving a second indication of physical possession of a payment card by a merchant. The authentication includes receiving a purchase request for an authorization of exchange from the payment account of the cardholder to the merchant and assigning a transaction identifier to the request for the authorization of the exchange. The authentication includes transmitting the request for authorization of the exchange from the cardholder payment account to the merchant and the transaction identifier. The authentication includes receiving an indication that an authentication identifier is associated with the transaction identifier. The authentication includes receiving a copy of the authentication identifier, facilitated by the cardholder. The authentication includes receiving validation that the copy of the authentication identifier matches the authentication identifier.

Authentication includes determining that a cardholder payment account is associated with a mobile device. Authentication includes receiving an indication of physical possession of a payment card. Authentication includes receiving a purchase request for an authorization of an exchange of funds from the cardholder account to the merchant. Authentication includes receiving a randomized transaction identifier to the request for the authorization of the exchange. Authentication includes transmitting to the mobile device, information associated with the request. Authentication includes transmitting to the mobile device, a request for confirmation of the authorization from the cardholder from the account of the cardholder to the merchant. Authentication includes receiving an indication, facilitated by the cardholder, that the exchange is authorized. Authentication includes authorizing the exchange of from the payment account of the cardholder to the merchant.

Methods and apparatus are provided for reducing the overall radiation hardness of a semiconductor chip. A radiation detector and a failure memory are provided. A disable signal or signals is produced by the failure memory. The disable signal is a required input to a user logic function, such as an off chip driver, an off chip receiver, a clock, or a static random access memory. When the radiation detector detects radiation, that detection is stored in the failure memory. The disable signal, when active, causes some or all of the user function to be inoperative. This invention is particularly important when the semiconductor chip is produced in a silicon on insulator (SOI) Complementary Metal Oxide Semiconductor (CMOS) process, which is naturally radiation resistant.

Method and apparatus to make a semiconductor chip susceptible to radiation failure

An electronic circuit and a method of designing the electronic circuit having conductive fill stripes which are electrically attached to the power distribution or to the signal routing of the circuit. Preferably, the conductive fill stripes are electrically attached to the power distribution and are interspersed between the power buses and signal wires on the various metal layers to satisfy the metal density requirements of integrated circuit and chip manufacturing. The conductive fill stripes are added during the design process after the placement of the power distribution and signal routing so that electrical continuity between the conductive fill stripes and the connecting bus, metal density requirements, other design rules and logic verification can be completed as the rest of the chip is designed.

Placement of conductive stripes in electronic circuits to satisfy metal density requirements

A system and method for designing an integrated circuit device by selectively reducing power lines based on wiring demand of the device are provided. In one embodiment, a power demand value of a region of the device is determined and a wiring demand value of the region of the device is determined. Based on the wiring demand value and the power demand Value, power lines in the region are selectively reduced. These steps may be repeated for each region of the device and a new power line layout may be generated after stepping through each of the regions. The reduction of power lines may be repeated until an acceptable power line layout is produced. Based on this layout, detailed signal wiring can be performed. This technique can, for example, more efficiently allocate power lines and signal wires and increase the density of the integrated circuit chip.

Design of an integrated circuit by selectively reducing or maintaining power lines of the device

A multi-threaded memory (and associated method) for use in a multi-threaded computer system in which plural threads are used with a single processor. The multi-threaded memory includes: multi-threaded storage cells; at least one write decoder supplying information to a selected multi-threaded storage cell; and at least one read decoder accessing information from a selected multi-threaded storage cell. Each of the multi-threaded storage cells includes: N storage elements, where N.gtoreq.2, each of the N storage elements having a thread-correspondent content; a write interface supplying information to the intra-cell storage elements; and a read interface reading information from the intra-cell storage elements. At least one of the intra-cell read and write interfaces selects one of the thread-correspondent contents based at least in part by identifying the corresponding thread to achieve intra-cell thread-correspondent content selection.

Multi-threaded cell for a memory

The present invention involves a BICMOS logic switching circuit biased between upper and lower supply voltages. This circuit includes a CMOS logic circuit driven by a plurality of logic input signals. This logic switching circuit also has a driving circuit coupled to the CMOS logic switching circuit and includes an output node, a first bipolar transistor, and a second bipolar transistor. The first bipolar transistor is coupled in series with the second bipolar transistor with the output node therebetween for providing an output signal on the output node, wherein the second bipolar transistor has a base directly coupled to a field effect transistor switch coupled to the upper supply voltage. The field effect transistor switch is controlled by logic input signals. The circuit also includes a switching circuit coupled to the upper supply voltage, the lower supply voltage, and the output node for causing the output signal on the output node to swing fully between the upper and the lower supply voltages in response to changes in the logic input signals.

Growing community of inventors

Rochester, MN, United States of America

Michael James Rohn