Adeia Semiconductor Bonding Technologies Inc.

Agilent Technologies, Inc.

Other

Lensvector Inc.

Candescent Technologies Corporation

Candescent Intellectual Property Services, Inc.

Canon Kabushiki Kaisha

Sony Corporation

Advanced Technology Materials, Inc.

Avago Technologies Fiber IP (singapore) Pte. Ltd

Tessera Technologies Ireland Limited

Tessera LLC

Michael James Nystrom

Giles Humpston

Shiyou Pei

Roger W Barton

Bob Lee Mackey

Lawrence S Pan

Belgacem Haba

George B Hopple

David Bazeley Tuckerman

Douglas M Smith

Tigran Galstian

Vladimir Presniakov

Karen Asatryan

Stephen C Wallace

Kollengode S Narayanan

Donald R Schropp, Jr

Bahram Afshari

James C Dunphy

Armen Zohrabyan

Gary Richard Trott

Xueping Xu

John M Macaulay

Yoshikatsu Ichimura

Kenneth Allen Honer

Peter P Clark

Daniel J Miller

Sudhakar Gopalakrishnan

Sergei Y Yakovenko

Nancy M Mar

Vage Oganesian

Christopher J Spindt

Ramamoorthy Ramesh

Annette Claire Grot

Amir Tork

Duane A Haven

David Ovrutsky

Aram Bagramyan

Christopher J Curtin

Jesse B Thompson

David R Morris

Andrey Grinman

Igor L Maslennikov

Randolph S Gluck

Charles Rosenstein

Gloria E Hofler

Christopher Wade

Jun Liu

Behzad Khodadad

Osher Avsian

John K O'Reilly

Charles White

Felix Hazanovich

Vasil M Chakarov

Heidi Linch Reynolds

Yulia Aksenton

Robert Burtzlaff

Avi Dayan

Ilya Hecht

Tomoo Kosugi

Mitchell Hayes Reifel

C Girvin Harkins

Viktor Konovalov

Rubin Ma

Methods and apparatus for testing operation of a single or multiple tunable active optical device(s) operated by one or more driving electrodes are described. Test methods and apparatus are provided for device testing without necessarily requiring direct physical contact with the driving electrodes. Testing subjects devices to incident light along an optical path and to an external electric field applied to the device producing a dipolar charge distribution within the electrodes, causing the device to operate. The effect of device operation on incident light is optically sensed. The sensed effect is analyzed to identify device defects. Test methods and apparatus are provided for testing multiple unsingulated devices during fabrication employing a strip contact structure having contact strips connected to multiple devices and extending to wafer edges, such that singulating devices leaves portions of the strip contact structure exposed on device dice edges providing electrical contacts in use.

Method and apparatus for testing operation of an optical liquid crystal device

A method of forming a microelectronic assembly includes positioning a support structure adjacent to an active region of a device but not extending onto the active region. The support structure has planar sections. Each planar section has a substantially uniform composition. The composition of at least one of the planar sections differs from the composition of at least one of the other planar sections. A lid is positioned in contact with the support structure and extends over the active region. The support structure is bonded to the device and to the lid.

Microelectronic assembly with multi-layer support structure

A tunable liquid crystal optical device is described. The optical device has an electrode arrangement associated with a liquid crystal cell and includes a hole patterned electrode, wherein control of the liquid crystal cell depends on electrical characteristics of liquid crystal optical device layers. The optical device further has a circuit for measuring said electrical characteristics of the liquid crystal optical device layers, and a drive signal circuit having at least one parameter adjusted as a function of the measured electrical characteristics. The drive signal circuit generates a control signal for the electrode arrangement.

Calibration of tunable liquid crystal optical device

Methods and apparatus for testing operation of a single or multiple tunable active optical device(s) operated by one or more driving electrodes are described Test methods and apparatus are provided for device testing without necessarily requiring direct physical contact with the driving electrodes Testing subjects devices to incident light along an optical path and to an external electric field applied to the device producing a dipolar charge distribution within the electrodes, causing the device to operate The effect of device operation on incident light is optically sensed The sensed effect is analyzed to identify device defects Test methods and apparatus are provided for testing multiple unsingulated devices during fabrication employing a strip contact structure having contact strips connected to multiple devices and extending to wafer edges, such that singulating devices leaves portions of the strip contact structure exposed on device dice edges providing electrical contacts in use.

A tunable liquid crystal optical device defining an optical aperture and having a layered structure. The device includes a film electrode formed on a surface of a first substrate and covered by a second substrate, and a contact structure filling a volume within the layered structure and contacting the film electrode. The contact structure is located outside of the optical aperture and provides an electrical connection surface much larger than a thickness of the film electrode, such that reliable electrical connections may be made to the electrode, particularly in the context of wafer scale manufacturing of such a device.

Contact structure for a tunable liquid crystal optical device

Packaged microelectronic elements are provided. In an exemplary embodiment, a microelectronic element having a front face and a plurality of peripheral edges bounding the front face has a device region at the front face and a contact region with a plurality of exposed contacts adjacent to at least one of the peripheral edges. The packaged element may include a plurality of support walls overlying the front face of the microelectronic element such that a lid can be mounted to the support walls above the microelectronic element. For example, the lid may have an inner surface confronting the front face. In a particular embodiment, some of the contacts can be exposed beyond edges of the lid.

Wafer level chip packaging

A microelectronic device includes a chip having a front surface and a rear surface, the front surface having an active region and a plurality of contacts exposed at the front surface outside of the active region. The device further includes a lid overlying the front surface. The lid has edges bounding the lid, at least one of the edges including one or more outer portions and one or more recesses extending laterally inwardly from the outer portions, with the contacts being aligned with the recesses and exposed through them.

Wire bonded wafer level cavity package

The present invention provides an integrated circuit chip assembly and a method of manufacturing the same. The assembly includes a package element having a top surface and an integrated circuit chip having a top surface, a bottom surface, edge surface between the top and bottom surfaces, and contacts exposed at the top surface. The package element is disposed below the chip with the top surface of the package element facing toward the bottom surface of the chip. At least one spacer element resides between the top surface of the package element and the bottom surface of the chip. According to one embodiment, the at least one spacer element may form a substantially closed cavity between the package element and the integrated circuit chip. According to another embodiment, first conductive features may extend from the contacts of the chip along the top surface, and at least some of said first conductive features extend along at least one of the edge surfaces of the chip.

Chip assembly including package element and integrated circuit chip

The present invention relates to a camera module. The camera module includes a circuit panel having a top side, a bottom side and transparent region, the circuit panel having conductors. The module further includes sensor unit disposed on the bottom side of the circuit panel, and the sensor unit includes a semiconductor chip having a front surface including an imaging area facing in a forward direction in alignment with the transparent region and an imaging circuit adapted to generate signals representative of an optical image impinging on the imaging area. The module further includes posts protruding from the bottom side of the circuit panel, wherein at least some of the posts being engagement posts having bottom surfaces, and at least some of the bottom surfaces abutting an engagement surface of the sensor unit.

Pin referenced image sensor to reduce tilt in a camera module

A method of forming a wall structure in a microelectronic assembly includes selectively depositing a flowable material on an upper surface of a first element in the microelectronic assembly, positioning a molding surface in contact with the deposited flowable material and controlling a distance between the upper surface of the first element and the molding surface with one or more objects positioned between the upper surface and the molding surface.

Method of forming a wall structure in a microelectronic assembly

A method of making chip assemblies includes providing an in-process assembly including a semiconductor wafer, a wafer compliant structure overlying a front surface of the wafer and cavities, and terminals carried on the compliant structure adjacent the cavities and electrically connected to the wafer, the cavities being substantially sealed. The method includes subdividing the in-process assembly to form individual chip assemblies, each including one or more chip regions of the wafer, a portion of the compliant structure and the terminals carried on the portion, and opening vents communicating with said cavities after said providing step.

Compliant terminal mountings with vented spaces and methods

A compliant structure is provided on a semiconductor wafer. The compliant structure includes cavities. The compliant structure and the wafer seal the cavities during process steps used to form conductive elements on the compliant structure. After processing, vents are opened to connect the cavities to the exterior of the assembly. The vents may be formed by severing the wafer and compliant structure to form individual units, so that the severance planes intersect channels or other voids communicating with the cavities. Alternatively, the vents may be formed by forming holes in the compliant structure, or by opening bores extending through the wafer.

A light-emitting device contains getter material () typically distributed in a relatively uniform manner across the device's active light-emitting portion. An electron-emitting device similarly contains getter material (, and) typically distributed relatively uniformly across the active electron-emitting portion of the device.

Light-emitting and electron-emitting devices having getter regions

Growing community of inventors

San Jose, CA, United States of America

Michael James Nystrom