Texas Instruments Corporation

Allegro Microsystems, LLC

Michael James Munroe

Thomas Ross

Angelo William Pereira

Sujan Kundapur Manohar

James McIntosh

Jiwei Fan

Mingyue Zhao

Logan G Stewart

Stephen Isaac Brink

Stephen Marshall

Pinar Korkmaz

Siyuan Zhou

Junhong Zhang

Daniel Alexander Katz

Described herein is a method and apparatus for an optical system configured to output redundant outputs, where the optical system includes at least one optical device configured to receive an optical signal; at least one optical transducer, wherein each at least one optical transducer is configured to receive the optical signal from the at least one optical device and convert the optical signal to an electrical signal; and at least one electronic device configured to receive each electrical signal and output the redundant outputs.

Optical system for improved reliability and performance

A converter circuit includes a power stage circuit configured to convert an input voltage received by an inductor to an output voltage provided at an output; a control circuit configured to generate input pulses to control the power stage circuit; a slope compensation circuit configured to provide a compensation signal to the control circuit for overcoming a sub-harmonic oscillation in the converter circuit, wherein the control circuit is configured to generate the input pulses based at least in part on the compensation signal; a slope compensation adjustment circuit configured to determine a rate of change of a current at the inductor and to provide a slope compensation adjustment signal based on the determined rate of change; and a modulation circuit configured to modulate the compensation signal with the slope compensation adjustment signal to produce the adjusted slope compensation signal.

Power converter with slope compensation

In one aspect, a gate driver circuit includes a gate driver having a first input connected to a first node and a second input connected to a second node. The gate driver circuit also includes a current source circuit that includes a first transistor and a capacitor having a top plate connected to the source of the first transistor and a bottom plate connected to ground. The gate driver circuit further includes a switch that includes a second transistor. A gate of the second transistor is connected to a drain of the first transistor and a source of the second transistor is connected to the first node.

Switch turn on in a gate driver circuit

In one aspect, a gate driver circuit includes a clamp circuit connecting a first node to a second node. The clamp circuit is configured to provide a clamp voltage. The gate driver circuit also includes a first driver connected to the first node and to the second node. The first driver comprising a first input configured to receive the clamp voltage from the clamp circuit. The gate driver circuit further includes a first transistor having a drain connected to the first node, a source connected to a circuit output and a gate connected to an output of the first driver. The first transistor has a gate-to-source voltage and an output voltage of the circuit output does not exceed the clamp voltage less the gate-to-source voltage of the first transistor.

Gate driver circuit providing an output voltage that is clamped

A device for averaging a sensed current includes a sampling circuit that samples at least two sampling points of each cycle of a front-end alternating current (AC) sensed signal. The two sampling points is substantially symmetrical with respect to a midpoint of each respective cycle of the front-end AC sensed signal. The device also includes a timing circuit that controls a timing of the sampling circuit to sample the front-end AC sensed signal on the at least two sampling points based on a timing signal generated by the timing circuit. The device further includes an averaging circuit that averages the two sampling points for a given cycle of the front-end AC sensed signal to produce an average sensed current.

Apparatus and methods for processing sensed current

Aspects of the present disclosure provide for a method. In some examples, the method includes receiving a synchronization signal, dividing the synchronization signal to form a first divided signal and a second divided signal, generating a first ramp signal and a second ramp signal, setting a latch output to a logical high value when the first divided signal has a logical high value or a value of the first ramp signal exceeds a value of a reference signal, setting the latch output to a logical low value when the second divided signal has a logical high value or a value of the second ramp signal exceeds the value of the reference signal, generating a synchronization clock according to the latch output and an inverse of the latch output, and outputting the latch output or the synchronization clock as a clock signal based on a value of a synchronization active signal.

External and dual ramp clock synchronization

A programmable load transient circuit includes a switchable power device for coupling a DUT output to its non-control node in series with a current sense device. A feedback loop is between the current sense device and the power device's control node that includes an integrator including an amplifier coupled to receive a signal that is a function of an average load current (I) supplied by the DUT from the current sense device and to receive a reference voltage (Vref). The integrator provides an output drive voltage that is coupled to an input of a level shifter which receives a pulse signal or DC level at another of its inputs. The level shifter provides an output waveform or DC voltage to the power device's control node that is a function of I.

Programmable load transient circuit

A phase generation circuit is disclosed. The circuit includes a ramp generation circuit arranged to generate a ramp signal in synchronization with a synchronization clock signal. A phase selection circuit generates a reference signal in response to a phase selection signal. A comparator has a first input terminal coupled to receive the ramp signal and a second input terminal coupled to receive the reference signal. The comparator produces a phase clock signal at an output terminal.

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Londonderry, NH, United States of America

Michael James Munroe