Agere Systems Inc.

Agere Systems Guardian Corp.

Michael James Hunter

Hyun K Lee

Nevin C Heintze

Ambalavanar Arulambalam

Xing Zhao

Richard Joseph Byrne

Qian Xu

Silvester Tjandra

Eu Gene Goh

Zhi He

David E Clune

Yun Peng

Hakan I Pekcan

David Wayne Potter

Thomas Klucsarits

Described embodiments provide a server for transferring data packets of streaming data sessions between devices. The server includes an accelerator that, for received data packets, i) extracts header fields of the packets, ii) determines, based on the header fields, a destination for the packets, and iii) provides the packets to the destination. For data to be transmitted, the accelerator i) groups the data into packets, ii) generates header fields for the packets, and iii) provides the packets to the network. A memory arbiter manages accesses to memory that buffers data and stores keys corresponding to the data sessions. A storage medium stores media files corresponding to the data sessions. A key manager includes i) a first memory for storing a master key of the server, ii) a second memory for storing one or more keys corresponding to the data sessions, and iii) a processor to encrypt and decrypt data.

Method and apparatus for secure key management and protection

In one embodiment, the invention provides a method for repairing a defective storage device in a physical storage-device array having a plurality of storage devices. The method comprises the steps of identifying a disk error associated with the defective storage device; effecting an error recovery pause based on the disk error; processing one or more outstanding data storage or retrieval requests; and generating a new data storage request instructing the physical disk device array having the defective storage device to store valid data associated with the data storage or retrieval request corresponding to the disk device error, whereby the defective storage device is repaired.

Method and apparatus for repairing uncorrectable drive errors in an integrated network attached storage device

A bidirectional bus repeater is disclosed that connects individual segments of a bidirectional bus. The exemplary bidirectional bus repeater consists of a direction control block and a buffer block. The buffer block contains one pair of buffers for each bus bit and an extra pair associated with the indicator lines. Indicator lines are used by the direction control block based on activity on the bus to generate control signals (control-A and control-B) that control the state of the tri-state buffers. In an exemplary embodiment, each node must toggle the indicator line whenever the node drives the bus. When the bus is inactive, the control-A and control-B signals generated by the direction control block are both inactive because the voltages on both sides of the bidirectional bus repeater are the same. When the direction control block detects a change of voltage on the indicator line associated with one side of the bus (e.g., indicator-A associated with bus-A), the corresponding tri-state buffers are enabled. Thereafter, the opposite bus segment (bus-B) is driven by the repeater buffers, until the bus segment bus-B reaches the same logic level as the bus segment bus-A. The logic level on indicator-B also changes to the same logic level as indicator-A. Eventually, both segments of the bus wire and the indicator wires connected to the bidirectional bus repeater circuit are equal and the DC turns off the a control signal A (cntl-A).

Bidirectional bus repeater for communications on a chip

The invention is a method and apparatus for minimizing voltage swing on the BIT and {overscore (BIT)} lines of a static random access memory (SRAM), thus minimizing precharge time and READ time for the SRAM. In accordance with the invention, an enhanced sense amplifier is provided in the last column of the memory array. The enhanced sense amplifier detects when the differential voltage between the BIT and {overscore (BIT)} lines exceeds the minimum detectable threshold of the sense amplifier. In response to that event, it asserts a feedback line to the READ control circuitry which halts the read operation essentially as soon as the differential voltage between the BIT and {overscore (BIT)} lines reaches the minimum differential voltage detectable by the sense amplifier. The technique is adaptive and assures both accurate operation and minimal precharge and read access times across variations in temperature and other environmental conditions.

SRAM method and apparatus

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Mertztown, PA, United States of America

Michael James Hunter