Fujitsu Corporation

Texas Instruments Corporation

Western Digital Technologies, Inc.

Sandisk Technologies Inc.

Michael James

Shay Benisty

Yehuda Hahn

Avichay Haim Hodes

Liam Michael Parker

Matias Bjorling

Stephen J Bassett

Daniel D Woods

Kana Ono

John W Williams

Scott Richmond

A storage system includes one or more data storage devices, a PCIe switch coupled to the one or more data storage devices, and a controller unit coupled to the PCIe switch. The one or more data storage devices are DRAM-less. The controller unit includes a dynamic random access memory (DRAM) host memory buffer (HMB) controller and a DRAM pool or a controller memory buffer (CMB) controller, a root complex/port, and the DRAM pool. The DRAM pool includes one or more DRAM devices. The one or more data storage devices are configured to interact with the controller unit and store data to a DRAM of the DRAM pool of the controller unit.

Enterprise host memory buffer for DRAM-less SSD

The present disclosure generally relates to writing data to streams. A host device can instruct a data storage device to operate in implied streams mode such that the host device does not need to tell the data storage device the specific stream in which to write data. The data storage device would maintain a list of open append points of specific streams. Upon receiving a write command, the data storage device determines whether the write command is for an already open stream, and if so, write to the specific stream. If not, then the data storage device opens a new stream or write the data to an overflow stream.

Implied streams

A storage system includes one or more data storage devices, a PCIe switch coupled to the one or more data storage devices, and a controller unit coupled to the PCIe switch. The controller unit includes a dynamic random access memory (DRAM) host memory buffer (HMB) controller and a DRAM pool or a controller memory buffer (CMB) controller, a root complex/port, and the DRAM pool. The DRAM pool includes one or more DRAM devices. The one or more data storage devices are configured to interact with the controller unit and store data to a DRAM of the DRAM pool of the controller unit.

Enterprise host memory buffer

At least one rotating memory medium such as a hard disk is installed in a hard disk drive or the like. The disk drive has a controller, controller memory and one or more heads for writing and reading to and from one or both sides of the disk. The disk is scanned for defects as sector locations, servo wedges and other information are recorded on tracks on the disk. Some unused space is reserved around the track to compensate for the area lost to defects. If a defect is detected in a sector, the sector is split into first and second parts on either side of the defective space. The location of the defective space is recorded in the controller memory and is processed like a servo wedge. In this manner, only part of the sector is lost due to the defect.

Methods and apparatus for formatting memory media

Data requested from a disk drive by a host is read continuously from sectors in tracks on a rotating disk and is temporarily stored in buffer memory within the disk drive. Before releasing the sectors for host access, each sector is checked for errors, and if errors are identified, error correction is attempted in a correction engine, using a selected error correction facility. If the errors are not corrected using the first selected correction facility, the bad sector is held in the buffer memory until the correction engine is idle. The correction engine is idle, for example, when good sectors (which have no errors) are read and are immediately released for host access. This idle time in the correction engine is used to attempt error correction using one or more different correction facilities. If the errors are corrected using the correction engine's idle time, it is not necessary to re-read the sector.

Methods and apparatus for correcting errors in data read from a disk drive

When data is read from a disk and stored in volatile memory, check bits are generated and stored in the memory using an algorithm such as cyclical redundancy check (CRC). The CRC algorithm operates on the basis of the bit length in which the data is organized, such as 8 bits. If the data has errors, an error correction code (ECC) algorithm is used to correct the data errors, but the ECC algorithm operates on the basis of symbols having a different bit length, such as 10 bits. To avoid having to re-read the data from the volatile memory to adjust the CRC value, the CRC algorithm is executed on selected mask data developed by the ECC algorithm, the CRC algorithm being executed on the basis of the second bit length to generate a CRC mask. The CRC mask corrects the stored CRC value.

Methods and apparatus for correcting data and error detection codes on the fly

A method for performing error correction code operations on data to be read from the disk ( ) of a hard disk drive ( ) includes applying a first error correction code algorithm to a first set of data to be written to the hard disk drive, and a second error correction code algorithm, different from the first, to a second set of data to be written to the hard disk drive ( ). The first and second error correction code algorithms may for example produce a different number of error correction code bits for application to said data. The selection between the first and second algorithms may be made, for instance, in dependence upon the physical locations ( ) on the disk, or in dependence upon the type of said data ( ) to be written. By reducing the number of ECC bits that need be associated with at least some of the data to be written to the disk ( ), the available space on the disk for user data can be increased.

Error correction codes applied variably by disk zone, track, sector, or content

A mass data storage device ( ) and method for operating it are disclosed. The mass data storage device has a rotating disk memory ( ) which has a number of sectors for containing data. A FIFO memory ( ) has three memory sections ( ), each for containing an entire sector of data associated with respective sectors of the rotating disk memory. An ECC unit ( ) has random access to any data contained in the FIFO memory ( ). The ECC unit ( ) is operated to perform error correction on data while the data is contained in the FIFO memory ( ). A FIFO memory controller ( ) controls locations at which data is written into and read from the FIFO memory ( ), and locations at which data correction is performed by the ECC unit ( ), so that as data is written into a first portion of the memory containing a sector currently being written, the ECC unit concurrently accesses a second portion of the memory containing a sector previously written to correct data therein, and data that has already been corrected by the ECC unit in a third portion of the memory is concurrently being read from the memory.

Growing community of inventors

Longmont, CO, United States of America

Michael James