Motorola Corporation

Freescale Semiconductor,inc.

Certicom Corporation

Other

Nxp Usa, Inc.

Michael J Torla

James Douglas Dworkin

Scott Alexander Vanstone

Ashok Vadekar

Robert John Lambert

Rodney C Tesch

P Michael Glaser

Thomas E Tkacik

Steven D Millman

John Michael Buss

Robert I Foster

Philipp Michael Glaser

David Abdoo

Frank James

Steve D Millman

Methods and systems are disclosed for anti-replay protection for network packet communications. A scorecard is stored that includes packet sequence numbers for received packets associated with a network packet flow. For each received packet, an anti-replay unit accesses the scorecard for an initial check to determine if the current packet represents a late packet and/or a replay packet. After further processing, the anti-replay unit accesses the scorecard for a final check to determine if the current packet represents a replay packet. For one embodiment, the initial check uses a first window of packet sequence numbers, and the final check uses a second window of packet sequence numbers that is larger than the first window. For further embodiments, multiple processing units operate in parallel to process received packets and to share the anti-replay unit, and each processing unit requests initial and final checks for received packets it processes.

Anti-replay protection for network packet communications

Embodiments of an electronic circuit comprise a module, such as a security module, configured to perform cryptographic processing for a predetermined security protocol that includes random number checking. The security module is controlled by a descriptor that includes instructions that cause the security module to access a generated random number, compare the generated random number to a random number stored during a previous execution of the descriptor, and generate an error signal when the generated random number and the previous execution random number are equal.

Cryptographic processing with random number generator checking

A technique for producing a hashed output of an input message according to any number of hash algorithms (e.g. SHA-256, SHA-348, SHA-512) having varying bit widths is described. At least a portion of the input message is stored in a first group of registers each having a bit width equal to a first bit width (e.g. 32 bits). If the selected hash algorithm has a larger bit width (e.g. 64 bits), a remainder of the input message is stored in a second plurality of registers each having a bit width equal to the first bit width. The hashed output is then computed according to the selected hash algorithm.

Systems and methods for efficient generation of hash values of varying bit widths

A result value, such as a parity value, for a set of corresponding data elements from a plurality of storage devices is determined using a commutative operation. When accessing the set of corresponding data elements from a plurality of storage devices, a dual access can be performed for the storage device accessed last for the set of corresponding data elements so as to also obtain a data element from the last-accessed storage device for the next parity calculation. As a result, the number of storage device accesses can be reduced compared to conventional systems whereby a single access is performed for each storage device to obtain a single data element from the storage device.

Optimization of storage device accesses in RAID systems

One embodiment relates to a data processing system having a cryptographic unit. The cryptographic unit includes cryptographic circuitry which performs a first cryptographic function to provide security for a portion of the cryptographic unit, and which performs a second cryptographic function to provide security for a portion of the data processing system external to the cryptographic unit. The cryptographic unit may therefore operate in a normal operating mode and in a secure operating mode. During a first secure operating mode a first key is used to decrypt first security configuration information which includes a second key. During a second secure operating mode, the second key is used to decrypt second security configuration information. The cryptographic unit may include a secure internal memory such that during the secure operating modes, the cryptographic unit may only process descriptors provided from this secure internal memory.

Method and apparatus for providing security in a data processing system

A Message Digest Hardware Accelerator (MDHA)for implementing multiple cryptographic hash algorithms such as the Secure Hashing Algorithm 1 (SHA-1), the Message Digest 4 (MD4) algorithm and the Message Digest 5 (MD5) algorithm. A register file () is initialized to different data values. A function circuit () performs logical operations based on the selected algorithm and provides a data value to a summing circuit () that is summed with mode dependent constant values selected from registers (and), round and step dependent data words generated by a register array block () to calculate the hash value for a text message stored in registers ().

Circuit for generating hash values

An integrated cryptographic system ( ) executes a mathematical algorithm that computes equations for public-key cryptography. An arithmetic processor ( ) receives data values stored in a temporary storage memory ( ) and computes both the Rivest-Shamir-Adleman (RSA) and Elliptic Curve Cryptography (ECC) algorithms. Multiplication cells ( and ) have an INT/POLY terminal that selects a C-register ( ) for computing RSA modular exponentiation or ECC elliptic curve point multiplication.

Multiplier cell and method of computing

A co-processor ( ) executes a mathematical algorithm that computes modular exponentiation equations for encrypting or decrypting data. A pipelined multiplier ( ) receives sixteen bit data values stored in an A/B RAM ( ) and generates a partial product. The generated partial product is summed in an adder ( ) with a previous partial product stored in a product RAM ( ). A modulo reducer ( ) causes a binary data value N to be aligned and added to the summed value when a particular data bit location of the summed value has a logic one value. An N RAM ( ) stores the data value N that is added in a modulo reducer ( ) to the summed value. The co-processor ( ) computes the Foster-Montgomery Reduction Algorithm and reduces the value of (A*B mod N) without having to first compute the value of &mgr; as is required in the Montgomery Reduction Algorithm.

Circuit and method for fast modular multiplication

A system for efficiently controlling the exchange of data between a host bus (,) and an input/output (I/O) register (,) of an elliptic curve (EC) processor (,) having a much wider datapath than that of the host device (,) . A spreading/despreading pattern is determined which spans multiple bit positions of the input/output register (,). In one embodiment, a full combinational circuit (,) is provided to connect a bit position of the host bus (,) to a bit position of the input/output register (,). In another embodiment, a combinational circuit (,) and an intermediate register (,) are provided. In still another embodiment, a spreading-by shifting system (,) is provided which comprises a plurality of subfield modules (,) into which data from the host bus (,) is shifted. The spreading/despreading pattern is achieved through multiplexers (,) connected between the subfield modules (,). In yet another embodiment, a cross bar switch (,) is provided to connect any bit position of the host bus (,) to any bit position of the I/O register,. In each embodiment, an EC control unit (,) is provided which stores information for the spreading/despreading pattern.

System for controlling data exchange between a host device and a processor

A finite field multiplier with intrinsic modular reduction includes an interface unit (,) that translates an n bit wide data path to a m bit wide data path where n is less than m. Also included is a finite field data unit (,) with m bit wide registers that is coupled to a finte field control unit (,). The finite field control unit (,) includes a microsequencer (,) and a finite state machine multiplier (,). The microsequencer (,) controls the finite state machine multiplier (,) which performs a finite field multiply operation with intrinsic modular reduction and presents a finite field multiplication product to the finite field data unit (,).

Finite field multiplier with intrinsic modular reduction

An elliptic curve (EC) processor circuit (,) comprising a finite field arithmetic logic unit (,), operation registers (,) an EC control unit (,) and a register file (,). A storage element (,) is coupled to the finite field arithmetic logic unit (,). The EC control unit (,) controls the various components of the EC processor circuit (,) to decompress a compressed one-bit representation of a Y coordinate of an elliptic curve point (X, Y). The EC control unit (,) controls the use of the operation register (,), the storage element (,) and the finite field arithmetic logic unit (,) to recursively compute the decompressed version of the compressed Y coordinate based upon the X coordinate and the compressed one-bit representation of the Y coordinate. The circuit and method employ minimal additional hardware and processing in an EC processor circuit (,).

Circuit and method for decompressing compressed elliptic curve points

A co-processor (,) executes a mathematical algorithm that computes modular exponentiation equations for encrypting or decrypting data. A pipelined multiplier (,) receives sixteen bit data values stored in an A/B RAM (,) and generates a partial product. The generated partial product is summed in a summer (,) with a previous partial product stored in a product RAM (,). A modulo reducer (,) causes a binary data value N to be aligned and added to the summed value when a particular data bit location of the summed value has a logic one value. An N RAM (,) stores the data value N that is added in a modulo reducer (,) to the summed value. The co-processor (,) computes the Foster-Montgomery Reduction Algorithm and reduces the value of (A*B mod N) without having to first compute the value of &mgr; as is required in the Montgomery Reduction Algorithm.

Circuit and method of modulo multiplication

A finite field inverse circuit has a finite field data unit (1112) and an inverse control unit (1110). The inverse control unit includes (1110) a k.sub.l and k.sub.u decrementer pair (1108, 1122), a k.sub.l -k.sub.u difference unit (1106), an inverse control finite state machine (1102), and a one-bit memory (1104) coupled to the inverse control finite state machine (1102). The finite field data unit (1112) includes four m bit wide registers that are shift registers designated as B (1120), A (1118), M (1114), and C (1116), where B- is a first register, A- is a second register, M- is a irreducible polynomial register, and C- is a field element register. An the irreducible polynomial is loaded left justified in the M-register, a field element to be inverted is loaded left justified in the C-register, and a single '1' is loaded in an LSB bit of the B-register. The field element is then inverted in 2n+2 system clock cycles where n is a field size associated with the field element.

Finite field inverse circuit

A Galois Field arithmetic logic unit (GF ALU) circuit (200) that generates a GF product of size M includes a first and a second input field element register (205, 210), a result field element register (215), a plurality, I, of subfield sets of logic gates (255, 260, 265), a plurality, S, of extension sets of logic gates (270, 275), and 3M switches (135). M is equal to S multiplied by I. A Galois Field of size M, S, and I each has an optimal normal basis. The first and second input field element registers (205, 210) are alternately coupled to the result field element register (215) by the I subfield sets of logic gates (255, 260, 265) in a first configuration and by the S extension sets of logic gates (270, 275) in a second configuration. The 3M switches (135) alternate the first and second configurations.

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Chandler, AZ, United States of America

Michael J Torla