Apple Inc.

Adobe, Inc.

Olio Devices, Inc.

Abobe Inc.

Michael J Smith

Tahoma Madrone Toelkes

Bernard Joseph Semeria

Dallas Blake De Atley

Josh P De Cesare

Joshua P De Cesare

Gordon J Freedman

Paul William Chinn

David Rahardja

Thomas Brogan Duffy, Jr

Manu Gulati

Simon P Cooper

Bruce Bartholomew Gaya

Peter Kiehtreiber

Jussi-Pekka Mantere

John William Scalo

Alexander Tony Maluta

Eugene Ray Tyacke

Timothy R Paaske

Ruchi Wadhawan

Joseph Sokol, Jr

Puneet Kumar

Jeffrey R Wilcox

Mitchell David Adler

Brijesh Tripathi

Nir Jacob Wakrat

Kenneth Louis Herman

Matthew John Byom

Shane J Keil

Gavin Peacock

R Stephen Polzin

Jonathan Jay Andrews

Fabrice L Gautier

Srinivas Annam

Joel N Kerr

Derek Fujio Iwamoto

Jacob Aaron Surber

Hardik K Doshi

Glenn Ruehle

Mark Edward Shepherd

Kerry J Kopp

George Comninos

Sedat Akkus

Joseph J Castro

Nayoung Kim

Lavanya Raghunath

Cynthia Kaschub

Joshua H Berlin

Glade Miller

Christopher J Noe

Gerard Richard Williams

Mark Hayter

Wei-Han Lien

Wade Benson

Shu-Yi Yu

Weihua Mao

David S Warren

Diarmuid P Ross

Steven Jacobs

Trip Vest

Kyle Dell'Aquila

Evan Wilson

Aj Cooper

Michael Miller

In one embodiment, a system includes a non-volatile memory that may serve as both the main memory system and the backing store (or persistent storage). In some embodiments, the non-volatile memory is divided into a main memory portion and a persistent portion. Data in the main memory operation may be encrypted using one or more first keys, and data in the persistent portion may be encrypted using one or more second keys, in an embodiment. The volatile behavior of main memory may be implemented by discarding the one or more first keys in a power down event or other event that indicates a loss of main memory data, while the one or more second keys may be retained. In one embodiment, the physical address space of the non-volatile memory may be a mapping from a second physical address space that is used within the system.

Unified addressable memory

One embodiment provides for a data processing system comprising multiple independent processors to execute multiple operating system environments of the data processing system, the multiple operating system environments to enable operation of multiple regions of a computing device associated with the data processing system. The multiple operating system environments are interconnected via a transport agnostic communication link. In response to detection of a fatal error in one or more of the multiple operating system environments, the multiple operating system environments coordinate performance of multiple separate error handling operations within the multiple operating system environments to generate a combined error log. The combined error log includes operational states of the multiple operating system environments.

Coordinated panic flow

Disclosed herein are systems, methods, and non-transitory computer-readable storage media for erasing user data stored in a file system. The method includes destroying all key bags containing encryption keys on a device having a file system encrypted on a per file and per class basis, erasing and rebuilding at least part of the file system associated with user data, and creating a new default key bag containing encryption keys. Also disclosed herein is a method of erasing user data stored in a remote file system encrypted on a per file and per class basis. The method includes transmitting obliteration instructions to a remote device, which cause the remote device to destroy all key bags containing encryption keys on the remote device, erase and rebuild at least part of the file system associated with user data, and create on the remote device a new default key bag containing encryption keys.

System and method for wiping encrypted data on a device having file-level content protection

Techniques are disclosed relating to data storage. In various embodiments, a computing device includes first and second processors and memory having stored therein a first encrypted operating system executable by the first processor and a second encrypted operating system executable by the second processor. The computing device also includes a secure circuit configured to receive, via a first mailbox mechanism of the secure circuit, a first request from the first processor for a first cryptographic key usable to decrypt the first operating system. The secure circuit is further configured to receive, via a second mailbox mechanism of the secure circuit, a second request from the second processor for a second cryptographic key usable to decrypt the second operating system, and to provide the first and second cryptographic keys.

Multiple mailbox secure circuit

Techniques for sharing style information between different applications and/or devices are provided. A document is displayed in a first window of a first application. The document includes user-selectable portions that each comprises at least one style information item. A menu is displayed in a second window. The menu provides a mechanism to store at least one style information item from the user-selectable portions. In response to a user selecting a user-selectable portion, menu options are provided in the menu to store at least one style information item for the selected user-selectable portion. The menu options are determined based on the style information item corresponding to the selected user-selectable portion. In response to the user selecting a menu option, the style information item corresponding to the selected menu option is stored.

Cloud-based inter-application interchange of style information

Techniques for sharing design elements between different applications and/or devices are provided. A design element is received from a first application as multiple representations, each of the multiple representations corresponding to a complementary storage format for the design element based on a design element type. The design element is stored as the multiple representations in a centrally stored library, the centrally stored library being shared among a plurality of applications. An indication to use the design element in a second application may be received. At least one of the multiple representations may be returned, as determined by the second application.

Cloud-based storage and interchange mechanism for design elements

An interface emulator for an IC is disclosed. An interface emulator includes a first first-in, first-out memory (FIFO) and a second FIFO. The first FIFO is coupled to receive data from an access port and a second FIFO coupled to receive data from at least one functional unit in the IC. The access port may be coupled to a device that is external to the IC. The external device may write information into the first FIFO, and this information may subsequently be read by a functional unit in the IC. Similarly, the functional unit may write information into the second FIFO, with the external device subsequently reading the information. Information may be written into the FIFOs in accordance with a predefined protocol. Thus, a particular type of interface may be emulated even though the physical connection and supporting circuitry for that interface is not otherwise implemented in the IC.

Interface emulator using FIFOs

In an embodiment, an integrated circuit includes at least one processor. The processor may include a reset vector base address register configured to store a reset vector address for the processor. Responsive to a reset, the processor may be configured to capture a reset vector address on an input, updating the reset vector base address register. Upon release from reset, the processor may initiate instruction execution at the reset vector address. The integrated circuit may further include a logic circuit that is coupled to provide the reset vector address. The logic circuit may include a register that is programmable with the reset vector address. More particularly, in an embodiment, the register may be programmable via a write operation issued by the processor (e.g. a memory-mapped write operation). Accordingly, the reset vector address may be programmable in the integrated circuit, and may be changed from time to time.

Persistent relocatable reset vector for processor

Resource restrictions are associated with a user identifier. A resource restriction agent receives operating system calls related for resources and provides resource request data to a resource agent. The resource agent determines whether the resource is restricted based on the resource request data and resource restriction data and generates access data based on the determination. The resource restriction agent grants or denies the system call based on the access data.

Resource restriction systems and methods

Method and apparatus of emulating interfaces using FIFOs

Data processing systems with interrupts and methods for operating such data processing systems and machine readable media for causing such methods and containing executable program instructions. In one embodiment, an exemplary data processing system includes a processing system, an interrupt controller coupled to the processing system and a timer circuit which is coupled to the interrupt controller. The interrupt controller is configured to provide a first interrupt signal and a second interrupt signal to the processing system. The processing system is configured to maintain a data structure (such as, e.g., a list) of time-related events for a plurality of processes, and the processing system is configured to calise the entry of a value, representing a period of time, into the timer circuit. The timer circuit is configured to cause an assertion of the first interrupt signal in response to an expiration of the time period.

Methods and systems for time keeping in a data processing system

Growing community of inventors

San Francisco, CA, United States of America

Michael J Smith