Advanced Micro Devices Corporation

Qualcomm Incorporated

Wisconsin Alumni Research Foundation

Sandbridge Technologies, Inc.

Ati Technologies Ulc

Aspen Acquisition Corporation

Advances Micro Devices, Inc.

Michael J Schulte

Nuwan S Jayasena

Gabriel H Loh

C John Glossner

Michael Ignatowski

Erdem Hokenek

Mayan Moudgill

Manish Arora

James Michael O'Connor

Srilatha Manne

Yasuko Eckert

Lisa R Hsu

William Lloyd Bircher

Madhu Saravana Sibi Govindan

Bradford Michael Beckmann

Nam Sung Kim

Ganesh Suryanarayan Dasika

Pablo Balzola

Angela Beth Dalton

Valentina Salapura

Greg Sadowski

Dimitri Tan

Carl E Lemonds

Sriram Sundaram

Sanjay Pant

Stephen Kushnir

William C Brantley

Youngtaek Kim

Vijay Janapa Reddi

Syed Gilani

Lloyd Bircher

Mahdu S S Govindan

Robert D Kenney

John D Thompson

Nandini Karra

Liang-Kai Wang

Pablo I Balzola

An accelerator device includes a first processing unit to access a structure of a graph dataset, and a second processing unit coupled with the first processing unit to perform computations based on data values in the graph dataset.

Flexible, scalable graph-processing accelerator

A multi-die semiconductor package includes a first integrated circuit (IC) die having a first intrinsic performance level and a second IC die having a second intrinsic performance level different from the first intrinsic performance level. A power management controller distributes, based on a determined die performance differential between the first IC die and the second IC die, a level of power allocated to the semiconductor chip package between the first IC die and the second IC die. In this manner, the first IC die receives and operates at a first level of power resulting in performance exceeding its intrinsic performance level. The second IC die receives and operates at a second level of power resulting in performance below its intrinsic performance level, thereby reducing performance differentials between the IC dies.

Multi-die system performance optimization

Some die-stacked memories will contain a logic layer in addition to one or more layers of DRAM (or other memory technology). This logic layer may be a discrete logic die or logic on a silicon interposer associated with a stack of memory dies. Additional circuitry/functionality is placed on the logic layer to implement functionality to perform various computation operations. This functionality would be desired where performing the operations locally near the memory devices would allow increased performance and/or power efficiency by avoiding transmission of data across the interface to the host processor.

Computation memory operations in a logic layer of a stacked memory

Various apparatus and methods using phase change materials are disclosed. In one aspect, a method of operating a computing device that has a first semiconductor chip with a first phase change material and a second semiconductor chip with a second phase change material is provided. The method includes determining if the first semiconductor chip phase change material has available thermal capacity. If the first semiconductor chip phase change material has available thermal capacity then the first semiconductor chip is instructed to operate in sprint mode. The first semiconductor chip is instructed to perform a first computing task while in sprint mode.

Distributed computing with phase change material thermal management

Durations of power management states are predicted on a per-process basis. Some embodiments include storing, in one or more data structures associated with one or more processes, information indicating previous durations of a power management state associated with the process(es). Some embodiments also include predicting a subsequent duration of the power management state for the process(es) using information stored in the data structure(s).

Predicting power management state duration on a per-process basis and modifying cache size based on the predicted duration

A method and device for reducing power during an instruction lane divergence includes idling an inactive execution lane during the lane divergence.

Method and apparatus for power reduction during lane divergence

A high-power-efficiency multiplier combines a standard floating-point multiplier with a power-of-two multiplier that performs multiplications by shifting operations without the need for floating-point multiplication circuitry. By selectively steering some operands to this power-of-two multiplier, substantial power savings may be realized. In one embodiment, multiplicands may be modified to work with the power-of-two multiplier introducing low errors that may be accommodated in pixel calculations.

High efficiency computer floating point multiplier unit

The described embodiments include a computing device with an entity (a processor, a processor core, etc.) and a controller. In these embodiments, the controller, using an idle duration history, predicts a duration of a next idle period for the entity. Based on the predicted duration of the next idle period, the controller configures the entity to operate in a corresponding idle state.

Configuring idle states for entities in a computing device based on predictions of durations of idle periods

The described embodiments include a computing device with one or more entities (processor cores, processors, etc.). In some embodiments, during operation, a thermal power management unit in the computing device uses a linear prediction to compute a predicted duration of a next idle period for an entity based on the duration of one or more previous idle periods for the entity. Based on the predicted duration of the next idle period, the thermal power management unit configures the entity to operate in a corresponding idle state.

Using a linear prediction to configure an idle state of an entity in a computing device

A system and method are presented. Some embodiments include a processing unit, at least one memory coupled to the processing unit, and at least one cache coupled to the processing unit and divided into a series of blocks, wherein at least one of the series of cache blocks includes data identified as being in a modified state. The modified state data is flushed by writing the data to the at least one memory based on a write back policy and the aggressiveness of the policy is based on at least one factor including the number of idle cores, the proximity of the last cache flush, the activity of the thread associated with the data, and which cores are idle and if the idle core is associated with the data.

Method and system for shutting down active core based caches

A multi-core data processor includes multiple data processor cores and a circuit. The multiple data processor cores each include a power state controller having a first input for receiving an idle signal, a second input for receiving a release signal, a third input for receiving a control signal, and an output for providing a current power state. In response to the idle signal, the power state controller causes a corresponding data processor core to enter an idle state. In response to the release signal, the power state controller changes the current power state from the idle state to an active state in dependence on the control signal. The circuit is coupled to each of the multiple data processor cores for providing the control signal in response to current power states in the multiple data processor cores.

Power control for multi-core data processor

A die-stacked memory device incorporates a reconfigurable logic device to provide implementation flexibility in performing various data manipulation operations and other memory operations that use data stored in the die-stacked memory device or that result in data that is to be stored in the die-stacked memory device. One or more configuration files representing corresponding logic configurations for the reconfigurable logic device can be stored in a configuration store at the die-stacked memory device, and a configuration controller can program a reconfigurable logic fabric of the reconfigurable logic device using a selected one of the configuration files. Due to the integration of the logic dies and the memory dies, the reconfigurable logic device can perform various data manipulation operations with higher bandwidth and lower latency and power consumption compared to devices external to the die-stacked memory device.

Die-stacked memory device with reconfigurable logic

Various stacked semiconductor chip arrangements and methods of manufacturing the same are disclosed. In one aspect, an apparatus is provided that includes a first semiconductor chip, a second semiconductor chip mounted on the first semiconductor chip, and a first portion of a phase change material positioned in a first pocket associated with the first semiconductor chip or the second semiconductor chip to store heat generated by one or both of the first and second semiconductor chips.

Stacked semiconductor chip device with phase change material

A system, method, and memory device embodying some aspects of the present invention for remapping external memory addresses and internal memory locations in stacked memory are provided. The stacked memory includes one or more memory layers configured to store data. The stacked memory also includes a logic layer connected to the memory layer. The logic layer has an Input/Output (I/O) port configured to receive read and write commands from external devices, a memory map configured to maintain an association between external memory addresses and internal memory locations, and a controller coupled to the I/O port, memory map, and memory layers, configured to store data received from external devices to internal memory locations.

Write endurance management techniques in the logic layer of a stacked memory

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Austin, TX, United States of America

Michael J Schulte