First Pass, LLC

Chaologix, Inc.

Michael J Schneiderwind

Douglas N Krening

Robert A Schneiderwind

Gregory B Lannan

Lark E Lehman

Steven Lee Kiel

Robert T Caffrey

A dynamically configurable logic gate includes an input summer for receiving a first input signal and a second input signal to generate a summed input signal. Further the dynamically configurable logic gate includes a nonlinear element that applies a nonlinear function to the summed input signal to produce a nonlinear output signal. The dynamically configurable logic gate output signal corresponds to one of a plurality of different logic gates responsive to adjusting the summed input signal and/or the nonlinear function. In another embodiment, the dynamically configurable logic gate includes feedback to one of the inputs. The dynamically configurable logic gate receives the two inputs and operates as one of a plurality of different logic gate types so as to produce an output signal that corresponds to a memory latch according to a selection of the control signal. An array structure of dynamically configurable logic elements is also disclosed.

Dynamically configurable logic gate using a non-linear element

A single chip application specific integrated circuit (ASIC) which provides a flexible, modular interface between a subsystem and a standard system bus. The ASIC includes a microcontroller/microprocessor, a serial interface for connection to the bus, and a variety of communications interface devices available for coupling to the subsystem. A three-bus architecture, utilizing arbitration, provides connectivity within the ASIC and between the ASIC and the subsystem. The communication interface devices include UART (serial), parallel, analog, and external device interface utilizing bus connections paired with device select signals. A low power (sleep) mode is provided as is a processor disable option.

Intelligent subsystem interface for modular hardware system

An apparatus and method for arbitrating requests for access to a shared resource. A buffer, on command from control logic, can selectively couple or decouple two buses. The control logic uses signals from two logic devices, one of which may be a microprocessor, and one of which may be a communications interface, to determine which of the devices is granted access to the shared resource. The control logic can generate an inhibit signal to the microprocessor to stall it while the second logic device is accessing the shared resource. Handshaking is used to control access by the second device to the shared resource.

Shared memory arbitration apparatus and method

Growing community of inventors

Castle Rock, CO, United States of America

Michael J Schneiderwind