Google Inc.

Weaved, Inc.

Xilinx, Inc.

Remot3.it, Inc.

Michael J S Smith

Suresh Rajan

David T Wang

Radoslav Danilak

Frederick Daniel Weber

Keith R Schakel

Michael Ward Johnson

Ryo Koyama

Wael Zohni

William P Schmidt

Hamish T Fallside

Jeremy Plunkett

Methods, systems, and computer program products for managing Internet of Things (IoT) network-connected devices.

Managing network connected devices

A method, system, and computer program product for Internet of Things (IoT) network-connected devices. Embodiments include methods and systems for registering one or more listener devices (e.g., mobile phones or tablets, etc.) to receive messages from one or more notification devices (e.g., web cameras, etc.). A notification server is selected from among multiple notification servers to receive notification messages from the notification devices and then to forward (e.g., through a push service, etc.) portions of or variations of the notification messages to the listener devices. In some embodiments, the selection of the notification server is based on load balancing between the multiple notification servers and/or push servers. In some embodiments, the selection of a notification server and/or push server is based on a provisioning file.

Techniques for the deployment and management of network connected devices

A method, system, and computer program product for network-connected devices.

Deploying and managing networked devices

A memory module, which includes at least one memory stack, comprises a plurality of DRAM integrated circuits and an interface circuit. The interface circuit interfaces the memory stack to a host system so as to operate the memory stack as a single DRAM integrated circuit. In other embodiments, a memory module includes at least one memory stack and a buffer integrated circuit. The buffer integrated circuit, coupled to a host system, interfaces the memory stack to the host system so to operate the memory stack as at least two DRAM integrated circuits. In yet other embodiments, the buffer circuit interfaces the memory stack to the host system for transforming one or more physical parameters between the DRAM integrated circuits and the host system.

Memory module with memory stack and interface with enhanced capabilites

In one embodiment, an interface circuit is configured to couple to one or more flash memory devices and is further configured to couple to a host system. The interface circuit is configured to present at least one virtual flash memory device to the host system, wherein the interface circuit is configured to implement the virtual flash memory device using the one or more flash memory devices to which the interface circuit is coupled.

System and method for increasing capacity, performance, and flexibility of flash storage

One embodiment of the present invention sets forth a heat spreader module for dissipating thermal heat generated by electronic components. The assembly comprises a printed circuit board (PCB), electronic components disposed on the PCB, a thermal interface material (TIM) thermally coupled to the electronic components, and a heat spreader plate thermally coupled to the TIM. The heat spreader plate includes an embossed pattern. Consequently, surface area available for heat conduction between the heat spreader plate and surrounding medium may be increased relative to the prior art designs.

Embossed heat spreader

Large capacity memory systems are constructed using stacked memory integrated circuits or chips. The stacked memory chips are constructed in such a way that eliminates problems such as signal integrity while still meeting current and future memory standards.

Methods and apparatus of stacking DRAMs

Memory module with memory stack and interface with enhanced capabilities

One embodiment of the present invention sets forth an abstracted memory subsystem comprising abstracted memories, which each may be configured to present memory-related characteristics onto a memory system interface. The characteristics can be presented on the memory system interface via logic signals or protocol exchanges, and the characteristics may include any one or more of, an address space, a protocol, a memory type, a power management rule, a number of pipeline stages, a number of banks, a mapping to physical banks, a number of ranks, a timing characteristic, an address decoding option, a bus turnaround time parameter, an additional signal assertion, a sub-rank, a number of planes, or other memory-related characteristics. Some embodiments include an intelligent register device and/or, an intelligent buffer device. One advantage of the disclosed subsystem is that memory performance may be optimized regardless of the specific protocols used by the underlying memory hardware devices.

Emulation of abstracted DIMMs using abstracted DRAMs

One embodiment of the present invention sets forth a memory module that includes at least one memory chip, and an intelligent chip coupled to the at least one memory chip and a memory controller, where the intelligent chip is configured to implement at least a part of a RAS feature. The disclosed architecture allows one or more RAS features to be implemented locally to the memory module using one or more intelligent register chips, one or more intelligent buffer chips, or some combination thereof. Such an approach not only increases the effectiveness of certain RAS features that were available in prior art systems, but also enables the implementation of certain RAS features that were not available in prior art systems.

Memory systems and memory modules

A memory module, which includes at least one memory stack, comprises a plurality of DRAM integrated circuits and an interface circuit. The interface circuit interfaces the memory stack to a host system so as to operate the memory stack as a single DRAM integrated circuit. In other embodiments, a memory module includes at least one memory stack and a buffer integrated circuit. The buffer integrated circuit, coupled to a host system, interfaces the memory stack to the host system so to operate the memory stack as at least two DRAM integrated circuits. In yet other embodiments, an interface circuit maps virtual addresses from the host system to physical addresses of the DRAM integrated circuits in a linear manner. In a further embodiment, the interface circuit maps one or more banks of virtual addresses from the host system to a single one of the DRAM integrated circuits. In yet other embodiments, the buffer circuit interfaces the memory stack to the host system for transforming one or more physical parameters between the DRAM integrated circuits and the host system. In still other embodiments, the buffer circuit interfaces the memory stack to the host system for configuring one or more of the DRAM integrated circuits in the memory stack. Neither the patentee nor the USPTO intends for details set forth in the abstract to constitute limitations to claims not explicitly reciting those details.

An FPGA-based communications access point and system for reconfiguration of the FPGA via a communications channel are described in various embodiments. One embodiment includes a physical interface circuit, a storage element (e.g., a RAM), an FPGA, and a configuration control circuit. The physical interface circuit is arranged for connection to a communications channel and is coupled to the FPGA. The configuration control circuit includes a controlling circuit (e.g., a PLD) and a memory circuit (e.g., a PROM). The PROM is configured with an initial configuration bitstream for the FPGA. The initial configuration bitstream implements both a communications protocol and a control function that writes configuration bits received by the FPGA via the communications channel to the RAM. The control function also generates a reconfiguration signal responsive to a first predetermined condition. The PLD is configured to load the initial configuration bitstream from the PROM into the FPGA, and, responsive to the reconfiguration signal from the FPGA, to load a second configuration bitstream from the RAM into the FPGA. The control function may be configured to interact with standard network programs such as FTP (file transfer protocol) or custom programs.

Growing community of inventors

Palo Alto, CA, United States of America

Michael J S Smith