Picker International, Inc.

Other

Michael J Petrillo

David C Oliver

James M Kapcio

Frank C Valentino

Frederick C Mailey

John F Vesel

Joseph Y Pai

Steven E Cooke

To calibrate a nuclear camera, the scintillation crystal (10) is irradiated with a uniform flood source (34). Scintillation events cause corresponding electrical pulses from photomultiplier tubes (12) that are optically coupled to the scintillation crystal. A selection circuit (40) compares (42) the amplitude or energy of pulses at each coordinate with a median energy and divides the pulses to generate a higher energy image (44) and a lower energy image (46). When the higher and lower energy images are subtracted (50) regions of the difference image (52) with high count densities identify a photomultiplier tube for gain adjustment. A gain adjustment circuit (60) monitors the amplitude of the electrical pulses and the number of pulses with each amplitude from the selected photomultiplier tube to generate a raw data energy distribution curve (FIG. 3). The energy distribution curve is smoothed (70) and the first derivative is taken (72). The curve is filtered (74) to isolate a preselected energy region. The curve is analyzed (92) to determine an energy value corresponding to a centroid (94) of the filtered first derivative curve. The centroid energy value is compared (96) with the centroid energy value from a preprogrammed table (32). The deviation between the calculated and looked-up centroid energy addresses a look-up table (98) which retrieves the appropriate adjustment to the selected photomultiplier tube. Each adjustment of the photomultiplier tube is stored in a gain adjustment history memory (110).

Technique for balancing anger cameras using an externally irradiated

A system for processing image data including a plurality of groups of dam values includes a memory for storing at least one difference vector for controlling an output of a display; means for generating each of the difference vectors as a function of a minimum data value and a maximum dam value included within a corresponding group of the clam values; and means for outputting each difference vector from the memory means to produce an image on a display.

Rasterization of line segments using difference vectors

A DMA control device (10) is connected with an n-bit address bus (12) by way of a bidirectional internal n-bit bus (14). The m most significant bits of signals received on the bidirectional bus (14) are reserved for carrying codes which identify or enable the DMA device to respond, to generate a load signal, to generate a count signal, and to generate an output signal. The remaining bits are reserved for address data. The load signal causes the remaining bit addresses to be loaded into counters (22) or registers (40). The count signal causes the counters (22) or a latched incrementor (44) to increment. The output signal controls three-state buffers (24, 42, 46) which cause the current address to be outputted on the bidirectional bus. In this manner, the DMA control device has only a single bus and in the embodiment of FIG. 2 replaces the counter array with a register array.

Direct memory access control device for use with a single n-bit bus with

An automatic apparatus for teeing golf balls for practice hitting includes a ball container, an indexer rocker wheel, a ball positioner, and a tee. The indexer rocker wheel carries a ball from an intake position at the container to a discharge position over the ball positioner, and returns for another ball. The ball positioner includes a reversible drive motor and a ball carrier for movement back and forth between a ball pickup position at the indexer to a ball delivery position on the tee. The tubular tee includes a photosensor operatively connected to the drive motor and responsive to light to signal the operation of the ball positioner.

Electro-mechanical teeing apparatus for golf balls

A system is provided for a display of CT cine images stored in a hybridized memory including both dynamic random access memory (14) and video random access memory frame buffer (16). The system includes memory address space which is allocated between the VRAM and DRAM. Non-linear, chained direct memory access control (22) provides a system to write a series of 640.times.512 pixel images directly from the frame buffer at 60 frames per second. The chaining provides a means for skipping over unused addresses at the end of a display line, thus maximizing utilization of expensive VRAM memory.

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Euclid, OH, United States of America

Michael J Petrillo