Intel Corporation

Motorola Corporation

Standard Microsystems Corporation

Michael J Pennell

David B Harnishfeger

Mark R Bohm

Venkat Iyer

Mitchell Beck

John Todd West

Shawn Shaojie Li

Akhlesh Nigam

An Automatic System Clock Detection System (ASCDS) may provide integrated circuits (ICs) with the capability to detect the frequency of an external crystal oscillator or clock source, and adjust the IC's internal PLL accordingly for proper IC operation. The frequency detection and PLL adjustment may be performed without any additional pins on the IC, and/or without requiring any additional external information. The ASCDS may be configured with an internal ring oscillator, which may be generated from standard logic elements, a watchdog counter, and an input clock counter. When the IC comes out of power on reset (POR), the ASCDS may compare the input clock counter with the watchdog counter, and determine the clock frequency of the input clock. It may then set the PLL parameters to ensure correct IC operation.

Automatic system clock detection system

An improved USB connection is disclosed that includes a pair of host parallel resistors connected to the USB connection at the host termination and a pair of peripheral parallel resistors connected to the USB connection at the peripheral termination. During high speed operation, the parallel resistors are switched to ground. Another aspect of the present invention is a voltage pull up apparatus for a USB connection. The apparatus includes a pull down resistor connected to the USB connection, a trickle current source attached to the USB connection, and a boost current source attached to the USB connection.

Dual termination serial data bus with pull-up current source

A differential amplitude detection circuit (10) passes the positive and negative components of a data communication differential signal through peak detector circuits (12) and (26), respectively. The peak detected voltages are held at first (15) and second (37) nodes by holding capacitors (14) and (28). Current loads (18) and (30) sink predetermined currents from the first and second nodes to prevent the peak voltages from becoming accumulated by the holding capacitors. The peak detected voltages are summed by summing circuit (21) to provide a signal V.sub.OUT that is absent of DC offset voltage errors that were present in the originally transmitted data signal. First and second resistors (36, 38) extract the common mode component of the input signal which may be subtracted from the V.sub.OUT signal for providing an error free true data output signal VTO.

Circuit and method of differential amplitude detection

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Phoenix, AZ, United States of America

Michael J Pennell