Texas Instruments Corporation

Michael J Overlaur

James L Conner

Rohit L Bhuva

Kevin L Kornher

Bao G Tran

Tracy S Paulsen

Herman A Groller

Jeffrey W Clark

A spatial light modulator (10) having a micromechanical active portion (12) encompassed by a light shield (14). The light shield (14) is fabricated upon a substrate (36) and has a plurality of openings (72, and 80) to permit underlying layers of photoresist (90, 92) to be undercut from beneath the light shield. Removal of the photoresist layers provides a sufficiently flat light shield, and eliminates the possibility that particles from the photoresist layer could migrate to beneath active micromirrors (30) of the spatial light modulator (12).

Spatial light modulator with improved light shield

A method of testing a large integrated circuit (10) of modular design. Test equipment is connected to a dedicated testing pad section (20) for each circuit section (22, 24, 34) of each module (12, 14, 16). The circuit section under test is tested via the testing pad adjacent that circuit section. The test equipment is then stepped to the testing section for the next circuit section. When testing is completed, the testing section is then electrically isolated from the circuit sections to prevent interference with operation of the entire circuit (10).

Large integrated circuit with modulator probe structures

The spatial light modulator (30) of the DMD type having associated memory cells (10) with a single bit line memory read back architecture (54). The memory cells (10) include a charge equalization switch (50) comprising a transistor connected across the bit lines (16,18) of the memory cell (10). This charge equalization transistor (50) is momentarily turned on (T.sub.3) to balance residual charge on the memory cell bit lines (16,18), after a write cycle (T.sub.2) but before the read cycle (T.sub.4). When the memory cell contents are subsequently read (T.sub.4), the memory cell contents will not change state. A single amplifier (54) is connected to one bit line for reading the memory cell contents. The single bit line (18) memory read back architecture provides a more efficient circuit layout to the spacing constraints required with DMDs, consumes less power than designs with a differential amplifier, and additionally, provides yield improvements.

Memory cell with single bit line read back

A large integrated circuit (10) of modular design, each module (12,14,16) having a circuit section (22,24,34) and a separate dedicated testing pad section (20). Each circuit module (12,14,16) can be individually functionally tested as an independent circuit with conventional prober equipment for defects. Each testing pad section (20) facilitates controlling the entire integrated circuit (10) so that the respective module circuit section (12,14,16) can be tested. Control circuitry (26) comprised of pass gates is provided to isolate the testing pad sections (20) from the operational portion (22,24,34) of the integrated circuit (10) when not under test. The present invention is ideally suited for large spatial light modulators, memory devices and other large sophisticated integrated circuits.

Large integrated circuit with modular probe structures

A method and device for controlling the bias voltages for a split-reset spatial light modulator. Each block of the spatial light modulator can be individually controlled lowering the throughput needed to load each frame of data. Blocks are selected individually or in groups with the potential of providing one voltage condition on the selected blocks and a different voltage condition on the deselected blocks. One embodiment of the disclosed method comprises input latches and buffers 44, address decode logic 46 to determine the selected blocks, mode select logic 48 to determine the requested operation, delay circuitry 50 to minimize current loading, and level shifters 52 to convert logic signals to voltage levels appropriate to control the output drive circuitry 54.

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Plano, TX, United States of America

Michael J Overlaur