Intel Corporation

Michael J Muchnick

Ryan Donovan Wells

Chinnakrishnan S Ballapuram

Altug Koker

Jasmin Ajanovic

Robert L Farrell

Zeev Offen

Ariel Berkovits

Jerry A Verseput

The present invention discloses a method comprising: sending cache request; monitoring power state; comparing said power state; allocating cache resources; filling cache; updating said power state; repeating said sending, said monitoring, said comparing, said allocating, said filling, and said updating until workload is completed.

Dynamic cache sharing based on power state

In one embodiment, the present invention includes a cache, compute engines connected to the cache, and a way mask disposed between the cache and the compute engines. This way mask may be partitioned into ways. Some of the ways may be dedicated to only one of the compute engines and other ways can be shared among more than one of the compute engines. Other embodiments are described and claimed.

A platform may comprise a core coherency domain, graphics coherency domain and a non-coherent domain. A graphics acceleration unit (GAU) of the graphics coherency domain may generate data units from an application and the data units may comprise display data units. The GAU may annotate the display data units with an annotation value before flushing the display data units to an on-die cache. The GAU may identify modified display data units among the display data units stored in the on-die cache and issue flush commands to cause flushing of the modified display data units from the on-die cache to a main memory. The display engine of the non-coherent domain may use the modified display data units stored in the main memory to render a display on a display device.

Ensuring coherence between graphics and display domains

A personal computer (PC) card insertion method and apparatus uses a subset of connector ground terminals and pins, located at either end of the connector, for detecting the onset of a card insertion. The host PC card slot connector has pull-up resistors for keeping the subset of ground terminals at a high logic level (V.sub.CC). Also, the subset of pins are made longer than the signal pins so that when an insertion of a PC card begins, the grounding of one or more of the subset of pins indicates that a PC card insertion has begun, allowing the host system to take the necessary precautions to ensure an orderly acceptance of the card without any undesirable system affects that might otherwise result. Also, a logic network for using the subset of connector terminals as additional grounding connections is provided upon completion of the insertion.

Growing community of inventors

Fair Oaks, CA, United States of America

Michael J Muchnick