International Business Machines Corporation

Globalfoundries Inc.

Michael J Lee

Bao G Truong

Visweswara Rao Kodali

Sam Gat-Shang Chu

Yuen H Chan

Peter Juergen Klim

Christopher McCall Durham

Jose Angel Paredes

Sam G Chu

Harsh D Sharma

Hema Ramamurthy

Geoffrey Wang

Juergen Pille

K Paul Muller

Rolf Sautter

Samuel I Ward

Vinod Ramadurai

Kevin A Batson

Ricardo H Nigaglioni

Douglas Ele Martin

Kevin Duc Tran

Visweswaya Rao Kodali

Eddie K Chan

Pre-comparing data in a dual compare content compact, low-leakage multi-bit content-addressable memory (CAM) cell is provided. A first compare input and a second compare input of a column in a dual compare content addressable memory ('CAM') device. A pre-compare signal is generated based on comparing the first compare input and the second compare input. A first polarity of the first compare input is compared with a first polarity a storage node data. A compare output of the first compare input is generated based on a logic state of the pre-compare signal. A first compare match is generated based on the compare output and a second compare match is generated based on the pre-compare signal.

Pre-compare operation for compact low-leakage dual-compare cam cell

Aspects of the invention include decoding a base address and an offset to generate a first potential memory address and a second potential memory address. A first cell data associated with the first potential memory address of a first partitioned array and a second cell data associated with a second partitioned array are evaluated. Carry-out bit information is received from a summing operation of the base address and the offset, the operating being performed in parallel to the decoding. The carry-out bit information is used to select either the first cell data or the second cell data.

Sum address memory decoded dual-read select register file

A compact, low-leakage multi-bit content-addressable memory (CAM) cell is provided. The CAM devices includes a transmission gate, having a positive field effect transistor ('PFET') and a negative field effect transistor ('NFET'), configured to compare a compare data input with storage node data having a first logic state. The CAM devices includes a passgate, in communication with the transmission gate, configured to compare the compare data input having a first logic state with the storage node data having a second logic state, wherein the passgate is an n-channel metal oxide semiconductor (NMOS) transistor and controls propagation of the compare data input, and the storage node data of a storage cell is used to control the passgate based on the storage node data. The CAM devices includes a PFET stack, having a first PFET and a second PFET, in communication with the transmission gate and the passgate, configured to compare the compare data input with the storage node data having the second logic state.

Compact low-leakage multi-bit compare CAM cell

Embodiments herein describe a SRAM that selectively flips received chunks of data from a high power state to a low power state before storing the chunks of data. The SRAM generates a flip bit for each of the data chunks stored in memory. The state of the flip bit varies depending on whether the corresponding data chunk was flipped before being stored in the SRAM. In one embodiment, the SRAM flips the bits in a data chunk before storing the bits only if all the bits are in the high power state. If so, the SRAM sets the flip bit for the data chunk to a first state and changes all the bits to the low power state before storing the data chunk. If not, the SRAM sets the flip bit to a second state and stores the data chunk without changing the states of the bits.

Reducing SRAM power using strategic data pattern storage

A trace array having features that provide reduced power consumption/power dissipation in processor circuits. The trace array circuit stores processor states during program execution and provides a resulting trace for subsequent analysis. The trace array includes power management features that, responsive to a control signal, reduce the power consumption of the trace array. A first state of the control signal indicates that the trace array circuit is storing states during the execution of the program and a second state of the control signal is set to enable the trace array for reading the collected states. The trace array may have dynamic read bit-lines and static write bit-lines to further reduce power consumption, and the pre-charge circuits that charge the dynamic read bit-lines may be selectively disabled in response to the first state of the control signal. Write-through may also be selectively disabled and optionally bypassed during state collection.

Reduced-power trace array for a processor

A mechanism is provided for enabling a proper write through during a write-through operation. Responsive to determining the memory access as a write-through operation, first circuitry determines whether a data input signal is in a first state or a second state. Responsive to the data input signal being in the second state, the first circuitry outputs a global write line signal in the first state. Responsive to the global write line signal being in the first state, second circuitry outputs a column select signal in the second state. Responsive to the column select signal being in the second state, third circuitry keeps a downstream read path of the cache access memory at the first state such that data output by the cache memory array is in the first state.

Preventing fast read before write in static random access memory arrays

A programmable Local Clock Buffer has a single inverter between the clock input and the delayed clock output. A transistor switch modulates the single inverter stage between a clock signal transmit state and a non-transmitting state. A combination of delay select bits control the timing of the beginning and ending of the transmit state of the inverter relative to the clock input via the transistor switch.

Low power programmable clock delay generator with integrated decode function

A mechanism is provided for gating a read access of any row in a cache access memory that has been invalidated. An address decoder in the cache access memory sends a memory access to a non-gated wordline driver and a gated wordline driver associated with the memory access. The non-gated wordline driver outputs the data stored in a valid bit memory cell to the gated wordline driver in response to the non-gated wordline driver determining the memory access as a read access. The gated wordline driver determines whether the data from the valid bit memory cell from the non-gated wordline driver indicates either valid data or invalid data in response to the gated wordline driver determining the memory access as a read access and denies an output of the data in a row of memory cells associated with the gated wordline driver in response to the data being invalid.

Cache array power savings through a design structure for valid bit detection

Mechanisms for multiple hit (multi-hit) detection in associative memories, such as a content addressable memory (CAM), are provided. The illustrative embodiments include a hit bitline that discharges as RAM side entries of the associative memory are accessed. The hit bitline is precharged high and pulled low by a series of devices that are activated as each RAM side row is accessed. As more RAM side rows are accessed, the hit bitline drops lower in voltage. The hit bitline drives an inverter with a threshold set such that any voltage equal to or lower than the threshold indicates a multi-hit situation. Any voltage higher than the threshold indicates a single hit or 'no-hit' situation. Thus, from the voltage of the hit bitline, the presence of a multi-hit condition may be detected.

Multi-hit detection in associative memories

A mechanism is provided for transparent multi-hit correction in associative memories. A content associative memory (CAM) device is provided that transparently and independently executes a precise corrective action in the case of a multiple hit being detected. The wordlines of a CAM array are modified to include a valid bit storage circuit element that indicates whether or not the corresponding wordline is valid or not. In operation, if multiple hits are detected, the multiple hit is signaled to the host system and the particular entries in the CAM array corresponding to the multiple hits are invalidated by setting their associated valid bit storage circuit elements to an invalid value or clearing the value in the associated valid bit storage circuit element. Any data returned to the host system as a result of the multiple hits is invalidated in the host system in response to the signaling of the multiple hits.

Transparent multi-hit correction in associative memories

A programmable local clock buffer for integrated circuit devices which is capable of varying initial settings is provided. The illustrative embodiments allow a single type of local clock buffer (LCB) to be used throughout an integrated circuit design while still being able to provide differing initial offsets and pulse widths for different local circuitry portions of the integrated circuit design. Delay circuit paths are provided, which provide discreet delay values, within the LCB that can be chained together when the LCB is instantiated to set the initial offset and pulse width values. When an LCB is instantiated in the integrated circuit device design, various ones of the delay circuit paths are connected together with the existing circuit paths of the LCB, i.e. the circuit paths that provide the pre-established offset and pulse width values, in order to set the initial offset and pulse width values for the LCB.

Programmable local clock buffer capable of varying initial settings

A system and method of selective row energization based on write data, with a selective row energization system including a storage arrayhaving M rowsand N columns; an N-bit data word register; a uniform-detect circuitresponsive to a data word to generate a uniform word data bit having a first value when the data word is uniform; an M-bit uniform-detect registerhaving M uniform-detect latches, each being associated with one of the M rowsand storing the uniform word data bit for the data word stored in the associated M row; and an M-bit row driver deviceresponsive to the uniform word data bit for each of the M rowsto inhibit energization of the M rowsfor which the uniform word data bit is the first value.

System and method of selective row energization based on write data

A mechanism for reducing the amount of power or energy consumed by an SRAM array when the SRAM array is being accessed is provided. Logic is provided that identifies a polarity of a row of memory cells whose data values are to be read. The polarity of the row of memory cells indicates whether a majority of the data values stored in the row of memory cells are logic 1 data values or logic 0 data values. Based on the polarity, selection logic either selects true data values or complement data values of the memory cells. Additional logic is provided in each memory cell for outputting a true data value to a read bit line and outputting a compliment data value to the read bit line based on the polarity.

Apparatus for SRAM array power reduction through majority evaluation

A D-Cache SRAM cell having a modified design in schematic and layout that exhibits increased symmetry from the circuit schematic and the physical cell layout perspectives. That is, the SRAM cell includes two read ports and minimizes asymmetry by provisioning one read port on a true side and one on the complement side. Asymmetry is additionally minimized in layout as cross coupling on both the true and complement sides rises up one level by providing from the local interconnect level a via connection to a M1 or metallization level. Moreover, the distance between the local interconnect (MC) and the gate conductor structure (PC) has been enlarged and equalized for each of the pFETs in the cross-latched SRAM cell. As a result, the SRAM cell has been rendered insensitive to overlay (local interconnect processing too close) by maximizing this MC-PC distance.

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Austin, TX, United States of America

Michael J Lee