Harris Corporation

Michael J Iacoponi

David K Vail, Jr

David F Seefeldt

A variable die size gate array architecture is realizable by forming in a semiconductor substrate an array of circuit devices separated from one another by a network of routing channels. Through the selective interconnection of the routing channels and the circuit devices a prescribed signal processing function may be implemented. The array of circuit devices includes gate supercells each of which is configurable to perform a respective signal processing operation, and input/output supercells each of which is configurable to effectively perform input/output interfacing between the gate supercells and signal terminals external to the array. The gate supercells and the input/output supercells are intermingled with one another in the array in accordance with a prescribed two-dimensional distribution pattern. Prescribed ones of the gate supercells and input/output supercells within at least one prescribed portion of the array are interconnected to effectively form an integrated circuit architecture capable of implementing the prescribed signal processing function. This portion is then separated from the wafer, and the integrated circuit architecture resident in the separated portion of the array is tab bonded to signal coupling terminals of an integrated circuit chip carrier by way of bonding pads on the input/output supercells.

Hierarchical variable die size gate array architecture

An apparatus and method for use in a communications system to modify a check word associated with a data word to retain the integrity of the former when the latter has been changed at a node in the system. When binary symbols are used, the received data word and the modified data word are combined on a serial bit-by-bit basis in a first exclusive OR gate. The result is encoded using the same coding scheme as used with the received data and check words. The encoded signal and the received check word are provided as an input to a second exclusive OR gate on a bit-by-bit basis. The signal produced by the second exclusive OR gate is the modified check word; the modified check word is then appended to the modified data word for transmission over the network. The entire process can be carried out on a bit-by-bit basis, allowing information to be relayed through a network node with minimal delay.

Growing community of inventors

Indian Harbor Beach, FL, United States of America

Michael J Iacoponi