Cisco Technology, Inc.

Other

International Business Machines Corporation

Michael J Healy

John T Chapman

Yi Tong Tse

Jason A Viehland

Alvar Antonio Dean

Daniel W Crocker

Denis Downey

John P Prokopik

Yuen-Wen Lee

Richard J Santarpio

Kevin J Twilliger

John A Flanders

Chachi Ching

Jeffrey Haskell Derby

Alon Shlomo Bernstein

Diana Lynn Orf

Pawel Piotr Sowinski

David Bryan Fox

Carl R Walker

David B Fox

Yihuan Sun

Achot Matevossian

Provided are techniques for a hardware accelerator with locally stored macros. A plurality of macros are stored in a lookup memory of a hardware accelerator. In response to receiving an operation code, the operation code is mapped to one or more macros of the plurality of macros, wherein each of the one or more macros includes micro-instructions. Each of the micro-instructions of the one or more macros is routed to a function block of a plurality of function blocks. Each of the micro-instructions is processed with the plurality of function blocks. Data from the processing of each of the micro-instructions is stored in an accelerator memory of the hardware accelerator. The data is moved from the accelerator memory to a host memory.

Hardware accelerator with locally stored macros

According to embodiments of the present invention, machines, systems, methods and computer program products for processing events including efficiently processing interrupt service requests for peripheral devices, such as hardware accelerators, utilized in parallel processing are provided. For each core engine of a peripheral device, the peripheral device detects whether one or more interrupt signals have been generated. Information associated with the one or more interrupt signals are stored in one or more registers of peripheral device memory, for each core engine. The information is aggregated and stored in a vector of registers in the peripheral device memory, and the aggregated information is written to memory associated with a CPU to enable CPU processing of interrupt requests from each core engine of the peripheral device.

Processing of events for accelerators utilized for parallel processing

A distortion device includes a transconductance stage, a current amplifier stage electrically coupled to the transconductance stage, and a transformer portion electrically coupled to the current amplifier stage. The transconductance stage includes a first capacitor to provide a ground to a resistor, and voltage across the resistor develops a current through a second capacitor to the current amplifier stage. The current amplifier stage includes a positive half cycle and a negative half cycle. The positive half cycle and the negative half cycle amplify the current from the transconductance stage and supply the amplified current to a primary winding of a transformer in the transformer portion, and the output of the transformer portion includes a low-level signal.

Inductive distortion system and method

A system and related methodology are provided that are configured to receive, at a first network element, multiple channels of video delivered as respective streams of packets, form a packet switched communication frame including a sub-layer header, encapsulate packets from the multiple channels of video into a payload field of the communication frame to obtain encapsulated packets, identify the encapsulated packets in the payload field with respective tags in the sub-layer header, designate the encapsulated packets in the payload field with respective launch values in the sub-layer header, and transmit the communication frame to a second network element. The first network element may be a universal edge quadrature amplitude modulator (UEQAM) and the second network element may be a relatively distant fiber node of a cable plant. The sub-layer header may also include Program Clock Reference (PCR) offset data that can be used for PCR re-stamping.

Multi-channel MPEG between headend and fiber node

A system, and related methodology, are provided that are configured to receive, at a first network element such as a Universal Edge Quadrature Amplitude Modulator (UEQAM), multiple channels of data delivered as respective streams of packets, form a packet switched communication frame including a sub-layer header, encapsulate packets from the respective multiple channels into a payload field of the packet switched communication frame, identify the packets encapsulated in the payload field with respective tags in the sub-layer header, and transmit the packet switched communication frame to a second network element such as a Downstream Physical (DS-PHY) entity where the individual packets are recovered and mapped to selected respective stream processing resources based on respective tags.

Transmission of multi-channel MPEG

A wideband cable modem system increases available bandwidth of a single channel by encoding a data stream into wideband packets. The wideband packets are associated with a logical wideband channel that extends over multiple physical downstream cable channels.

Wideband cable system

A door knocker including a front display piece that is in the form of an alpha character piece including a front facing surface for display of the alpha character and a rear facing surface having at least one rearwardly directed flange member that forms part of a pivot means for the front display piece, and a rear support piece that is adapted for attachment to the face of the door. The rear support piece includes at least a first leg for pivotal engagement with the flange member and forming another part of the pivot means, a second leg that is for attachment to the door, and a third leg that forms a knocker that is selectively engageable with the rear facing surface of the alpha character piece.

Door knocker

In one embodiment, a gateway between a variable delay network and a constant delay network receives over the variable delay network a plurality of data streams to be multiplexed over a modulated channel extending through the constant delay network. A first processing component of the gateway generates command-packet-descriptors corresponding to content packets included in the received data streams. A second processing component of the gateway uses transmit time indications included in the command-packet-descriptors to schedule transmission of modulated packets representing the received data streams over the modulated channel.

Intra channel video stream scheduling

An M-CMTS compatible UEQAM device implements circuitry to identify and analyze MAP message in the data stream sent from the M-CMTS Core with respect to timing information embedded in those messages. The improved UEQAM will then create a specific message as an extension to DEPI to communicate that information to the M-CMTS Core. The M-CMTS Core will employ that analysis to automatically adjust MAP message advance time to reduce delay and thus improve system performance. This invention will provide a closed-loop between the M-CMTS Core and the UEQAM where valuable transmission information will periodically be fed back from UEQAM-to-M-CMTS Core in real-time.

Map message expediency monitoring and automatic delay adjustments in M-CMTS

In one embodiment, a gateway for a constant delay network identifies a baseband clock that is synchronized by exchanging synchronization messages over a packet switched network. The gateway then generates a strobe by manipulating the identified baseband clock using a custom multiplier that is selected according to transmission variables. The gateway then signals a front end component to process fixed length packets for transfer to a back end component according to the generated strobe, which can reduce or eliminate buffering by the back end component and can improve cable modem operation.

Timed packet processing to regulate data transfer between components of a gateway for a constant delay network

A modular Cable Modem Termination System (CMTS) includes a packet shelf operating a Data Over Cable Service Interface Specifications (DOCSIS) Media Access Control (MAC) framer. One or more downstream Physical Interface (PHY) shelves receive DOCSIS data from the packet shelf over a packet switched network and modulate the DOCSIS data for sending on a downstream path of a cable plant. One or more upstream PHY shelves send DOCSIS data received from an upstream path of the cable plant over the packet switched network to the packet shelf. By separating the PHY components from the MAC and from the system software, the PHY components for a Hybrid Fiber Coax (HFC) plant may be replaced with different PHY components for other access technologies such as wireless, Digital Subscriber Lines (DSL), Ethernet-to-the-Home, Fiber-to-the-Home, or fiber Passive Optical Networks (PONs).

Downstream remote physical interface for modular cable modem termination system

Methods and devices are provided for allowing upstream and downstream cable modem termination systems to be located in different physical locations. According to some embodiments of the invention, a downstream CMTS is located at a head end of a cable network and an upstream CMTS is located in each of a plurality of hubs in a cable network. Such a configuration provides more flexibility than prior art systems, especially when much of the traffic passing through the downstream CMTS is broadcast traffic, such as IP video, that will be passed to multiple hubs. Such configurations are more economical because they do not require every hub to have its own downstream CMTS. In preferred embodiments, the upstream and downstream functions are synchronized using a Global Positioning System ('GPS') reference source.

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Berlin, MA, United States of America

Michael J Healy