Unisys Corporation

Michael J Hazzard

Gary C Wu

Chandra S Pawar

Edward J Pullin

Joseph C Duggan

Steven H Leibowitz

A microprocessor architecture that includes an arithmetic logic unit (ALU), a bit processing unit (BPU), a register file and an instruction register is disclosed. The BPU performs complex logical operations in a single clock cycle. The ALU continues to perform the slow arithmetic operations (e.g., multiply, divide). The BPU has two special purpose registers, a zero flag and a match flag, which are used for program execution control. The BPU performs bit manipulations on data stored in and received from the register file and/or individual fields in the instruction currently being executed by the BPU.

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Downingtown, PA, United States of America

Michael J Hazzard