Alcatel

Dsc Communications Corporation

Alcatel USA Sourcing, L.p.

Alcatel USA

Michael J Hanlon

Stephen A Deschaine

Robert S Gammenthaler, Jr

Richard Schroder

E Lawrence Read

Daniel P Lyon

Sharlene C Lin

Serge Francois Fourcand

Gary D Hanson

Robert W Cantwell

John C Bellamy

Russell L Humphrey

Nader Sabzevari

Michael A Vincze

Raymond K Driskill

Gregory L VanDePutte

Dwight K Patterson

Mohammad A Rahman

A signaling link interface ( ) includes a high level data link controller ( ) that receives signaling information from network elements in a telecommunication network. A link state controller ( ) performs message transfer part level two processing on the signaling information. The link state controller ( ) generates a response message that the high level data link controller ( ) provides back to the network elements. The high level data link controller ( ) and the link state controller ( ) are implemented in hardware as field programmable gate array devices. Information related to operation of the signaling link interface ( ) may be downloaded from a remote site into the field programmable gate array devices. The signaling link interface ( ) processes signaling information received from a plurality of signaling links on a link by link basis.

Signaling link interface for processing signaling information in a telecommunications network

In particular embodiments, the present invention provides a system for managing signaling messages in a telecommunication system. The system includes a first control module that is operable to receive signaling messages from a plurality of signaling links, process the signaling messages, and send the processed signaling messages through a communication network interface. The system also includes a second control module that is operable to receive the signaling messages from the plurality of signaling links, process the signaling messages, and send the processed signaling messages through a communication network interface. The system further includes a Matelink coupled to the first control module and the second control module. The Matelink is operable to communicate the status of the first control module to the second control module and the status of the second control module to the first control module. The first control module and the second control module are further operable to be in either an active mode or a standby mode, only one of the first control module and the second control module being in the active mode at one time, the control module in the active mode sending the processed signaling messages through the associated communication network interface and the status messages over the Matelink.

Method and system for providing redundancy for signaling link modules in a telecommunication system

A digital desynchronizer (10) includes an elastic store unit (12) that receives a synchronously mapped asynchronous data signal (14) and outputs asynchronous output data over an asynchronous output data signal (20) in response to an output clock signal (22). The output clock signal (22) is generated by a digitally controlled oscillator (24). The digitally controlled oscillator (24) receives a speed up signal (28) and a slow down signal (30) from a jitter accumulator (26) in order to adjust the clock rate of the output clock signal (22). The jitter accumulator (26) compares retimed read address information (32) to write address information (34) from the elastic store unit (12), subtracts an initial bias, adds the result to any previous sum, and compares this final result to programmable threshold levels in order to determine whether or not to assert the speed up signal (28) or the slow down signal (30). The clock rate of the output clock signal (22) is adjusted by a speed up factor, a slow down factor, or a nominal factor in response to the comparison of the read address information (32) and the write address information (34). The jitter accumulator (26) has programmable thresholds comprised of a lower threshold signal (72) and an upper threshold signal (76) to establish the rate of integration of the incoming jitter or wander. The asynchronous output data thus has a programmable logarithmically integrated frequency response.

Apparatus and method of desynchronizing synchronously mapped

A data conversion circuit is provided. The data conversion circuit includes a transceiver that can receive a first data channel in a first or second data format and convert it into a second data channel having a third data format. The transceiver can also receive data from the second data channel in the third data format and convert it into the first data channel in the first or second data format. The data conversion circuit includes a bus interface that is connected to the transceiver. The bus interface transfers data between the transceiver and a bus control module. The data conversion circuit also includes an onboard controller interface that is connected to the bus interface. The onboard controller interface transfers data between the transceiver and an onboard controller.

System and circuit for telecommunications data conversion

In the inbound direction, a tributary processor (32) includes an SPE encoder/decoder for extracting a synchronous payload envelope (SPE) from an STS-1P signal. A path terminator (62) may extract DS3 signals or a matrix payload envelope (MPE) from the STS-1P SPE. A DS1/DS3 extractor (68) generates DS1 signals from either the DS3 or MPE signals. An MPE mapper (70) creates MPE signals from the DS1 signals. A wideband stage interface (74) converts the MPE signals into matrix transport format (MTF) signals for cross-connection in a wideband center stage matrix (22). In the outbound direction, the wideband stage interface (74) receives MTF signals from the wideband center stage matrix (22) and generates MPE signals therefrom. The MPE signals are sent through the MPE mapper (70) in order to extract DS1 signals. The DS1 signals are converted to DS3 signals or another MPE mapping by the DS1/DS3 extractor (68). The path terminator receives DS3 or MPE signals for conversion into an STS-1P SPE. The SPE encoder/decoder creates the STS-1P signals from the STS-1P SPE for transmission to the appropriate interfaced subsystem or network.

Processor device for terminating and creating synchronous transport

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Plano, TX, United States of America

Michael J Hanlon