Motorola Corporation

Semiconductor Components Industries, LLC

Marvell International Limited

Marvellworld Trade Ltd.

Atmel Corporation

Michael J Gay

Johannes A Gutmann

W David Pace

Paolo Migliavacca

Philippe Goyhenetche

Frederic Declercq

Francois Louis Dorel

Loic Cunnac

A circuit comprises an antenna and a first port coupled to the antenna using a first reactive circuit. A first switching device is coupled across first and second input nodes of the first port, and configured to convey a signal across the first and second input nodes to a Near Field Communication (NFC) circuit in a first mode, and to isolate the NFC circuit from the antenna in a second mode. The antenna has a first resonance at a first frequency in a first mode and has a second resonance at a second frequency in a second mode. A second port is coupled to the antenna using a second reactive circuit. A rectifier has an input coupled to the second port and an output coupled to an energy storage device. A second switching device is coupled across the second port and configured to control an amount of current flowing through the rectifier by alternating between a first state and a second state at a third frequency when the circuit is in the second mode.

Wireless power interface using an NFC antenna

Systems, methods, and other embodiments associated with radio frequency identification (RFID) circuits are described. According to one embodiment, a radio frequency identification circuit includes an antenna network and an integrated circuit configured to operate as a reader and a tag in combination with the antenna network. The integrated circuit is configured to provide an output admittance determined by a ratio of current and voltage negative feedback signals such that a frequency response of the combined integrated circuit and antenna network is adjustable when operating as a reader.

Antenna interface for radio frequency identification circuit

Circuits, architectures, systems, and methods for generating temperature-stable reference voltages with offset compensation. The circuits generally include a diode junction voltage generator, and three composite voltage generators configured to operate in first and second phases or modes of operation. The diode junction voltage generator produces first and diode junction voltages with different current densities (Vdand Vd). The first composite voltage (VC) comprises at least a fraction of the first and/or second diode junction voltage. The second composite voltage (VC) is generated during the first phase and comprises a difference between Vdand a sum of VCand an offset voltage (Ve) of an amplifier and/or other summation circuit. The third composite voltage (VC) is generated during the second phase such that VCis proportional to a difference between Vdand a sum of Ve and VC. A temperature-stable reference voltage proportional to VCmay be continuously generated. Embodiments advantageously produce reference voltages much smaller than the band-gap voltage, are substantially insensitive to any voltage offset in the associated summation circuit, and/or produce low noise without further filtering.

Circuits, architectures, apparatuses, systems, and methods for low noise reference voltage generators with offset compensation

A DC-DC converter and method for compensating for errors in the DC-DC converter. The DC-DC converter includes an inductor coupled for receiving a source of operating voltage through a plurality of switches. The switches are controlled by a control circuit that has first and second circuit paths that are substantially parallel to each other. Each circuit path is comprised of two switched capacitor comparators that are connected in series. The circuit paths function such that during one portion of a clock period one of the circuit paths operates in an error correction mode and the other circuit path operates in a normal mode. During a different portion of the clock period the operational modes of the circuit paths switch. This allows for a calibration interval in a sampled system in which at least one circuit path is always active and responsive to the input signals in a desired manner.

DC-DC converter and method

The present invention provides shunt voltage regulation by employing a rectifying means to rectify an incoming signal and a current sinking means to divert current from the output of the rectifying means in such a way that the output voltage is maintained at an appropriate level and the modulation level does not rise above the acceptable range. This is accomplished by having two feedback mechanisms for the control of said current sinking means. A first feedback mechanism utilizes a voltage dividing means to generate a control voltage signal that will cause the average output voltage of the rectifying means to be equal to the a reference voltage. A second feedback mechanism utilizes non-linear processing means and capacitors to transmit part of the modulation frequency to the control of the current sinking means, thereby keeping the modulation at the output of the rectifying mean at an appropriate level at all time.

Interface for shunt voltage regulator in a contactless smartcard

In an exemplary embodiment, a system ( ) is formed to include a semiconductor device ( ) that is formed to function as a voltage regulator. The semiconductor device ( ) is formed to have a control loop that includes an amplifier ( ) and a feedback transistor ( ) that provide a small signal AC gain that varies inversely to a load current of an output transistor ( ) in order compensate for the manner in which the output transistor ( ) transconductance depends on the load current flowing through the output transistor ( ).

Method of forming a voltage regulator semiconductor device having feedback and structure therefor

A voltage regulator ( ) utilizes a first current source ( ) and a second current source ( ) to form a reference current to limit current flow through an output transistor ( ) during a start-up period. After the start-up period expires, the first current source ( ) is disabled and the voltage regulator ( ) controls the output voltage produced by the output transistor ( ) instead of controlling the current flow through the output transistor ( ).

Voltage mode voltage regulator with current mode start-up

A current sensing circuit ( ) for use in an ADSL interface circuit senses an input current (IL) flowing through a resistor (R ) and provides an image output signal at an output which is an image of the input current. The circuit comprises an input stage ( ) having a first input terminal for coupling to one terminal of the resistor (R ), a second input for coupling to the other terminal of the resistor and first ( ) and second ( ) output terminals, a first P-type current mirror ( ) having an input terminal, an output terminal and a supply terminal, the input terminal being coupled to the first output terminal ( ) of the input stage ( ) and the supply terminal being coupled to a first supply line, a second N-type current mirror ( ) having an input terminal, an output terminal and a supply terminal, the input terminal being coupled to the second output terminal ( ) of the input stage ( ) and the supply terminal being coupled to a second supply line and combining means ( ) coupled to the output terminals of the first and second current mirrors for combining the output signals at the output terminals of the first and second current mirrors to provide the image output signal. The circuit further comprises bias means (R , R ) for biasing the input stage to operate in class AB such that the input stage provides a transconductance which tends to increase with increasing level of the input current, and offset means (R , R , R ) for generating offset voltages in the first and second current mirrors which cause the gains of the current mirrors to tend to reduce with increasing level of the input current such that the combined gains of the input stage and the first and second current mirrors remain substantially independent of the level of the input current.

Current sensing circuit and ADSL interface circuit

A current sense circuit (100) for providing an output signal (Iout) representative of a current signal (Id) flowing through a FET output device (101) comprises a first transistor (102) for providing an image current signal (I.sub.m) which is substantially proportional to the current signal flowing through the FET output device (101) until the drain-source voltage signal of the FET output device (101) is less than a predetermined voltage and a second transistor (104) coupled to a control electrode of the first transistor (102) and for coupling to the gate electrode of the FET output device (101). The first (102) and second (104) transistors are matched and have the same threshold voltages as that of the FET output device (101). The second transistor (104) provides a correction current signal (I.sub.c) when the drain-source voltage signal of the FET output device (101) is less than the predetermined voltage. Subtracting circuitry (106) coupled to the first (102) and second (104) transistors subtracts the correction current signal (I.sub.c) from the image current signal (I.sub.m) to provide a corrected image current signal which is substantially proportional to the current signal flowing through the FET output device (101). The output signal (Iout) comprises the image current signal (I.sub.m) or corrected image current signal depending on the drain-source voltage of the FET output device (101).

Current sense circuit

A telephone apparatus for connection to central office equipment to receive a caller ID signal therefrom and having an operating mode in which line current is less than a threshold at which off-hook state is detected, the line current drawn in said mode being sufficient to allow reception and processing of the caller ID signal. In this way, the telephone apparatus can receive and process the caller ID signal, and so can determine whether the call can be accepted, without the central office equipment recognizing the apparatus as having gone off-hook (i.e. having already accepted the call).

Telephone apparatus for caller ID

In a telephone line interface circuit, a first transistor (Q1) is arranged in series in the signal line (3) and a second transistor (Q2) is arranged in parallel across the telephone line (3, 4), both transistors being controlled from a control circuit (5), so that, when the voltage across the telephone line falls below that required to keep the first transistor (Q1) in normal conduction, the second transistor (Q2) maintains the signal path. In order to reduce cross-over distortion, a negative feedback loop (Q5, R1, Q3, Q1) and supply voltage sensing means (6) controls the first transistor (Q1) so that it conducts only sufficient quiescent current to power the circuit, any remaining current being conducted by the second transistor (Q2), thereby maintaining both transistors in conduction down to low quiescent line current levels.

Telephone line interface circuit

A telephone line interface circuit has a transmit path for coupling to a telephone line and a receive path for coupling to the telephone line (2). The transmit path includes a first amplifier (A1) having an output for coupling to the line (2), a first input for receiving a signal to be transmitted and a second input for receiving a first sum signal made up of a.c. and d.c. line voltage signals plus a.c and d.c. line current signals. The feedback loop thus described has sufficient loop gain to constrain the first sum signal to be substantially equal to the signal at the first input. The receive path includes a second amplifier (A4) having a first input for receiving the first sum signal, a second input for receiving substantially twice a second sum signal made up of the a.c. and d.c. line current signals plus the d.c. line voltage signal/and an output for providing receive signals. The circuit thus presents a predetermined impedance to the telephone line (2) and also provides hybrid balance when the impedance of the line (2) is substantially equal to the predetermined impedance.

A clamp circuit is described in which a video signal is capacitively coupled to an amplifier which has enabled and disabled states. An operational amplifier receives the output of the amplifier and a reference voltage and the output of the operational amplifier is fed back to the inputs of both the amplifier and the operational amplifier. The loops may be selectively disconnected and the amplifier selectively disabled so that the output of the amplifier has the same level during each of three modes namely clamp mode when the video signal is known to be black, image mode during normal operation when the video signal returns to black, and during blank mode initiated at any other desired time.

Clamp circuit

The invention relates to a current mirror circuit (28) comprising: an input node (29); a first simple current mirror (30) of a first type, such as pnp bipolar technology, having an input coupled to said input node (29) and an output; a second simple current mirror (32) of a second semiconductor type, such as npn bipolar technology, having an input coupled to said output of said first simple current mirror and an output; a third simple current mirror (34) of said first semiconductor type having an input coupled to said output of said second simple current mirror and an output coupled to said input node (29); and an output node (31) coupled to said second simple current mirror (32) so as to receive the sum of the input and output currents of said second simple current mirror flowing in a common terminal thereof.

Current mirror

A sampled data circuit having: two or more serially connected sampled data stages (2) each comprising switching means (6) and storage means (10); and clock means (4) for applying to the switching means of consecutive stages clock signals of respectively first and second phases alternating between first and second levels,

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Vaud, Switzerland

Michael J Gay