Xilinx, Inc.

Rosemount Inc.

Allegro Microsystems, LLC

Polar Semiconductor, Inc.

Michael J Gaboury

David Erich Tetzlaff

David Jamie Haas

Gregory J Rausch

Michael C Doogue

Shaun D Milano

Shohei Osaka

Georges El Bacha

William P Taylor

Alexander Latham

Eric Douglas Groen

Matthew L Bibee

Gregory Delmain

Brian Taylor Brunn

Charles Walter Boecker

William C Black

Moises Emanuel Robinson

Brian Lee Westfield

Ramesh Harjani

Stephen D Anderson

Weston R Roper

David Glen Tyson

James P Ross

Thomas Kerdraon

Bernard L Grung

Khaldoun Bataineh

Michael Mass

Feng Wang

Xiaoxin Feng

Methods and apparatus for providing an integrated circuit having a drive current source, a magnetic sensing element coupled to the drive current source, the magnetic sensing element having first and second differential outputs, and first and second current elements to provide respective currents in relation to the drive current source, wherein the first current element is coupled to the first differential output and the second current element is coupled to the second differential output. In illustrative embodiments, an IC output can output a voltage corresponding to the currents of the first and second current elements.

Methods and apparatus for sensor diagnostics

In one aspect, a magnetic field sensor includes a chopper stabilized amplifier and a plurality of Hall-type elements in parallel and connected to the chopper stabilized amplifier. In another aspect, a magnetic field sensor includes a chopper stabilized amplifier and a plurality of Hall quad elements in parallel and connected to the chopper stabilized amplifier. In a further aspect, a current sensor has a bandwidth of 1 MHz and includes a chopper stabilized amplifier and a plurality of Hall quad elements, fabricated in silicon, in parallel and connected to the chopper stabilized amplifier.

Magnetic field sensor

Methods and apparatus for an integrated circuit having a magnetic sensing element, a fault detection module including circuitry to detect a fault condition and to self-test operation of the circuitry to detect the fault. The integrated circuit includes a fault pin to indicate the fault condition.

Methods and apparatus for a current sensor having fault detection and self test functionality

A method of controlling a power factor correction (PFC) converter having a first PFC sub-circuit and a second PFC sub-circuit determines when to transition the PFC converter between an interleaved mode and a saving energy mode (SEM). The method includes generating an amplified error signal based on a monitored output voltage of the PFC converter. The second PFC sub-circuit is disabled in response to the amplified error signal being less than a first threshold value and enabled in response to the amplified error signal exceeding a second threshold value.

Saving energy mode (SEM) for an interleaved power factor correction (PFC) converter

A controller provides frequency compression for an interleaved power factor correction (PFC) converter that determines the ON and OFF times of each switch associated with the PFC converter to prevent operating frequencies in the audible range. The controller includes a first circuit for generating an ON time current source having a magnitude related to an amplified error signal and the monitored input voltage, and a second circuit for generating an OFF time current source having a magnitude related to the ON time current source, the monitored input voltage, and the monitored output voltage. Gate drive circuitry provides gate drives signals to the switches of the interleaved PFC converter at a frequency determined by magnitudes of the ON time current source and the OFF time current source.

Frequency compression for an interleaved power factor correction (PFC) converter

The present invention provides a method of controlling an interleaved power factor correction (PFC) circuit operating in a discontinuous conduction mode (DCM). The controller employs a normal mode of operation in which inductor currents in each PFC sub-circuit are estimated based on the monitored input voltage and monitored output voltage, and switching devices associated with each PFC sub-circuit are controlled to ensure DCM operation. As the input voltage increases, the OFF times of each PFC sub-circuit increase such that the inductor currents no longer overlap. In response, the controller activates a time-limiting mode (TLM) in which OFF time durations for each sub-circuit are based on the monitored sum of load currents as opposed to the monitored input voltage and monitored output voltage.

Time-limiting mode (TLM) for an interleaved power factor correction (PFC) converter

A controller generates a drive signal for a converter circuit that includes an active component (i.e., transistor) that is selectively controlled to convert a rectified input to direct current (DC) output. The controller employs an outer feedback loop (based on monitored output voltage of the converter circuit), an inner feedback loop (based on monitored AC input current drawn by the converter circuit), and a pulse width modulator (PWM) to generate the drive signals necessary to generate the desired DC output voltage and to provide power factor correction to the converter circuit. In particular, the inner feedback loop includes an amplifier and a fault protection and clamp circuit. The amplifier has a first input connected to receive a feedback signal representing the monitored AC input current, a second input, and an output that provides a current feedback signal to the PWM. The fault protection and clamp circuit is connected to monitor the voltage at the second input of the PWM and to detect fault conditions associated with the converter circuit, wherein in response to an over-voltage condition at the second input or a detected fault condition the fault protection and claim circuit clamps the current feedback signal provided to the second input of the PWM to a reference value and provides the reference value in feedback to either the first or second input of the amplifier.

Protection and clamp circuit for power factor correction controller

A receiver has a first input port and a second input port both coupled to a differential amplifier through first and second input capacitors. A bias circuit coupled to the core side of the first input capacitor and to the core side of the second input capacitor is configured to provide a selected voltage to at least one of the first input and the second input of the differential amplifier. In one embodiment, a common mode bias circuit provides a common mode voltage to both inputs of a differential amplifier. In a particular embodiment, a run length detector monitors the output of the differential amplifier and provides a run length feedback signal or an average bit density feedback signal to the set the selected voltage between periods of data reception.

DC balance compensation for AC-coupled circuits

A device and a method for processing high data rate serial data includes a VCO initial frequency calibration circuit. The circuit includes a frequency detection block for indicating a difference between a reference clock and a divided VCO clock, a frequency calibration block that produces a digital output signal based upon the difference between the reference clock and the divided VCO clock, and a digital-to-analog converter for producing an analog VCO adjust signal. The frequency detection block produces a plurality of signals based upon the reference clock and the divided VCO clock. A plurality of user selected inputs selects a frequency detection lock range and hysteresis range and a coarse loop open calibration lock and hysteresis range. The frequency calibration block implements a state machine for producing the digital output signal that sets the initial operating frequency then adjusts the frequency of the VCO clock.

VCO initial frequency calibration circuit and method therefore

According to an example embodiment, a data-transfer circuit transfers high-speed input data toward an output port by coupling the data circuit selectively through a resistive-impedance circuit and a capacitive-impedance circuit to accommodate both high-frequency and low-frequency components of the input data signal. In a particular implementation, the control circuit can selectively control the data-passing circuit path by causing the input data to pass through the resistive-impedance circuit and therein pass low-frequency components of the input data signal while the capacitive-impedance circuit passes high-frequency components of the input data signal.

Selective signal coupling in high speed I/O circuits

Circuitry for equalizing a high data rate serial data stream that receives low frequency and high frequency test tones, accurately measures an amount of attenuation experienced by the high frequency test tone in relation to the low frequency test tone, and accordingly, produces equalization data that results in a corresponding amount of equalization or pre-emphasis being added to an outgoing signal. More specifically, however, the present invention includes both open loop and closed loop systems for equalizing or adding pre-emphasis to a signal with attenuation. In the open loop transceiver system, a presumption is made that an amount of attenuation in both the outgoing and ingoing directions are equal. In the closed loop transceiver system, a receiver determines an amount of equalization and produces the equalization data to a remote transceiver.

Method of adaptive equalization for high-speed NRZ and multi-level signal data communications

An integrated circuit ('IC') includes a phase-locked loop ('PLL') with a controllable oscillator embedded in the integrated circuit. A phase-lock circuit provides a lock control signal to the controllable oscillator; and a digital-to-analog converter (&#x201c;DAC&#x201d;) provides an oscillator adjustment signal to the controllable oscillator according to a digital code. The digital code is generated by an adjustment circuit configured in the fabric of a programmable logic device, or embedded in the IC, for example. In a particular embodiment, the DAC adjusts the PLL to reduce differential mode voltage in the phase-lock circuit.

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Burnsville, NM, United States of America

Michael J Gaboury