Apple Inc.

Cisco Technology, Inc.

Michael J Dhuey

Farid A Yazdy

Philip Roland Graham

Richard Thayer Wales

David C Buuck

Tark Abed

Ashok T Desai

Peter H J How

Randy K Harrell

Pete Lombrozo

Philip E Marechal

Andrew D Grunes

Ronald Ray Hochsprung

Peter HJ How

Reichard T Wales

A display device may reduce the latency of the display of a digital signal by reducing the latency that the display device adds to the digital signal. After a digital signal is received by an input module, the signal is stored in a frame buffer as a plurality of pixels. A controller determines the input frame rate of the digital signal and a pixel delay. The controller monitors the frame buffer to determine when the frame buffer has stored a number of pixels greater than or equal to the pixel delay. After the frame buffer contains enough pixels, the controller initiates transmission of the pixels from the frame buffer to a display module. In certain embodiments, the controller initiates transmission of the pixels to the display module before the frame buffer has stored all pixels corresponding to the frame.

Latency reduction in a display device

A system for enhancing eye gaze in a telepresence system includes a plurality of local cameras coupled to at least one local display. Each local camera is directed to at least one respective local user section and operable to generate an image of the respective local user section. The system also includes a plurality of remote displays. Each remote display is operable to reproduce the local video image of the local user section. Within the system the plurality of remote displays and the plurality of local cameras are aligned such that when a first local user within a local user section looks at a target at least one remote display is operable to reproduce the local video image of the first user section comprising the first local user such that the eye gaze of the reproduced image of the first local user is directed approximately at a corresponding target.

System and method for enhancing eye gaze in a telepresence system

A system and method are provided for capturing and transmitting frames in a video conference. The method comprises determining a frame rate and a shutter speed according to variable control data, capturing image data according to the determined shutter speed, and transmitting the captured image data through a communication interface to a remote video conference system. The variable control data specifies a relationship between the frame rate and the shutter speed.

System and method for dynamic control of image capture in a video conference system

A novel circuit for driving a fan includes an output terminal for supplying the fan with drive power, a pulse width modulation driver, and a limiter. A first power terminal of the fan is held at a first voltage (e.g., 0V), and a second power terminal of the fan is coupled to the output terminal of the driver circuit. The PWM driver provides a series of fan drive pulses on the output terminal, and the limiter prevents the voltage on the output terminal from falling below a predetermined voltage. The predetermined voltage is greater than the first voltage at which the fan's first power terminal is held, and is sufficient to keep the fan in motion even when the duty cycle of the PWM signal is 0%. In a particular embodiment the limiter includes a voltage clamp. In a more particular embodiment, the voltage clamp is a diode. In another particular embodiment the limiter includes a switch for combining a PWM signal with a DC voltage at an output.

Quiet fan speed control

A novel a circuit for driving a fan includes an output terminal for supplying the fan with drive power, a pulse width modulation driver, and a limiter. A first power terminal of the fan is held at a first voltage (e.g., 0V), and a second power terminal of the fan is coupled to the output terminal of the driver circuit. The PWM driver provides a series of fan drive pulses on the output terminal, and the limiter prevents the voltage on the output terminal from falling below a predetermined voltage. The predetermined voltage is greater than the first voltage at which the fan's first power terminal is held, and is sufficient to keep the fan in motion even when the duty cycle of the PWM signal is 0%. In a particular embodiment the limiter includes a voltage clamp. In a more particular embodiment, the voltage clamp is a diode. In another particular embodiment, the limiter includes a switch for combining a PWM signal with a DC voltage at an output.

Cache memory is managed to update the data stored in the cache regardless of whether the address being operated upon is designated as cache inhibited. In this way, the contents of the cache are coherent with main memory so that when the processor redesignates a noncacheable range of addresses to be cacheable, the cache does not need to be flushed. Read operations follow cache inhibit faithfully.

Cache management during cache inhibited transactions for increasing cache efficiency

An arrangement in which resistors are interposed on a bus line to attenuate reflected spurious pulses. The resistors are positioned on the bus so as not to be between a processor and its cache memory, but so as to be between the combination of the processor and cache memory and components such as a peripheral controller and a memory controller. The resistors reflect a portion of the pulse energy and attenuate the pulse energy passing through them. In another aspect of the invention, the traces making up the bus are arranged so that the intertrace distance is greater than a distance between the traces and an internal reference plane. This causes magnetic energy radiated by an aggressor trace to encounter the reference plane before it encounters a victim trace. This also reduces the amount of magnetic cross-coupling.

Enhanced signal integrity bus having transmission line segments

A sleep mode controller, useful for an electronic device such as a computer, can supply multiple clocks with appropriate synchronization and which is capable of dynamic speed switching. The device provides clock signals at various speeds and relationships which can in turn be used to support various functions of the electronic device. The sleep mode controller can be activated and smoothly transition various clock signals from one time domain to a second time domain, each of which has predetermined speeds and clock-signal relationships. Dynamic speed switching is used to reset timing (bus and processor clock) sensitive elements such that computer machine speed (bus and processor clock frequencies) can be changed dynamically without interruption of I/O services or general OS and application level functions.

Sleep mode controller for power management

A signal delay apparatus delivers synchronous signals over long and short traces. For a signal that needs to be delayed because it will be carried on a relatively short trace, passing the signal through a clocked device such as a flip flop will delay the output by a selected number of clocks. If a relatively longer trace is longer than the shorter trace by the distance a signal travels during the selected number of clock cycles, then clock signals over the respective paths will be synchronized. In a preferred embodiment, the signals are clock signals from a clock generator.

Digital signal distribution for long and short paths

Circuit arrangements and methods are disclosed for upgrading an 040-based personal computer system using an optional, peripheral add-in card. In one embodiment, the present invention comprises a PowerPC-based microprocessor, such as the MPC601, having one megabyte of on-board direct mapped level 2 external cache memory arranged as tag and data blocks. The PowerPC-based board is inserted into a processor-direct data path sharing the data and address bus with the 040 microprocessor. System random access memory (RAM), I/O, and other functional blocks are present on the main board comprising the 040-based computer. The MPC601 is coupled via address and data buses to the tag cache, a bus translation unit (BTU), a read only memory (ROM) storing the operating system code for the PowerPC microprocessor, the data cache, a dual frequency clock buffer, and other interface components such as a processor-direct data path including address and data latches. When the computer is turned on, the BTU coupled to the data bus sequentially clears all valid bits in the tag cache, whereafter the cache and memory map are enabled. The 040 processor on the main board is disabled after power-up by using the 040 JTAG test port after inactivating the power-on fast reset. By shifting in appropriate RESET, TCK, and TMS patterns, the 040 will be placed in a nonfunctional, high impedance state. However, DRAM present on the motherboard may be accessed by the 601 after a cache miss. DRAM is accessed via a 601-040 transaction translation operation within the BTU, wherein coded tables map the MPC601 transaction into the appropriate 040 transaction.

Methods and apparatus for controlling back-to-back burst reads in a

Methods and apparatus for translating incompatible bus transactions

A system in which line reflections in a clock distribution network are cancelled by providing the clock distribution network with a branching point and suitably arranging recipient devices with respect to the branching point to provide for clock pulse reflection cancellation and attenuation. Moreover, the system can be arranged so that clock pulse reflections are not received as pulses which are discrete from legitimate clock pulses. The system also provides capability for reducing electromagnetic interference.

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Cupertino, CA, United States of America

Michael J Dhuey