Qualcomm Incorporated

Brooktree Corporation

Microchip Technology Inc.

Nurlogic Design, Inc.

Artisan Components, Inc.

Prunolo, Inc.

Conexant Systems, Inc.

Nanohenry Inc.

Rapid Bridge LLC

Michael J Brunolli

Vaishnav Srinivas

David Ian West

Dexter Tamio Chun

Animesh Datta

Ohsang Kwon

Seid Hadi Rasouli

Mickael Malabry

Kamesh Medisetti

Mark Wayland

Christine Sung-An Hau-Riege

Behnam Malek-Khosravi

Sucheta Kumar Harish

Prathiba Balasubramanian

Nikolay Bomshtein

Behnan Malek-Khosravi

Nurtjahya Sambawa

Timothy Mowry Hollis

Patrick Isakanian

Chinh Luong Hoang

Stephen Thilenius

Michael D Wykes

Jungwon Suh

Eugene Robert Worley

Thomas Clark Bryan

Reza Jalilizeinali

Charles David Paynter

Sreeker Dundigal

Benjamin E Felts, Iii

Yu Huang

Paul N Katz

Evan Siansuri

Stephen G Glennon

Bernie Jord Yang

David A G Wilson

A CMOS device with a plurality of PMOS transistors each having a PMOS drain and a plurality of NMOS transistors each having an NMOS drain includes a first interconnect and a second interconnect. The first interconnect is on an interconnect level extending in a length direction to connect the PMOS drains together, and the second interconnect is on the interconnect level extending in the length direction to connect the NMOS drains together. A set of interconnects on at least one additional interconnect level physically couple the first interconnect and the second interconnect to an output of the CMOS device. A third interconnect on the interconnect level extends perpendicular to the length direction and offset from the set of interconnects. The third interconnect is capable of flowing current from the PMOS drains or from the NMOS drains to the output of the CMOS device.

Layout construction for addressing electromigration

A memory interface includes: a pull-up device and a pull-down device, wherein the pull-up device couples between a power rail and a data line, and wherein the pull-down device couples between the data line and ground; and a power supply configured to supply a first power supply voltage to the power rail during a terminated data transmission mode in which a receiving memory interface coupled to the data line has an active on-die termination, and wherein the power supply is further configured to supply a second power supply voltage to the power rail during an unterminated data transmission mode in which the on-die termination does not load the data line, the second power supply voltage being less than the first power supply voltage.

Memory interface with adjustable voltage and termination and methods of use

A CMOS device with a plurality of PMOS transistors and a plurality of NMOS transistors includes a first interconnect and a second interconnect on an interconnect level connecting a first subset and a second subset of PMOS drains together, respectively. The first and second subsets are different and the first and second interconnect are disconnected on the interconnect level. A third interconnect and a fourth interconnect on the interconnect level connect a first subset and a second subset of the NMOS drains together, respectively. The third interconnect and the fourth interconnect are disconnected on the interconnect level. The first, second, third, fourth interconnects are coupled together through at least one other interconnect level. Additional interconnects on the interconnect level connect the first and third interconnects together, and the second and fourth interconnects together, to provide parallel current paths with a current path through the at least one other interconnect level.

A system and method are provided for supplying bulk current to a voltage regulator embedded on a system-on-chip (SoC). An embedded voltage regulator (EVR) supplies a regulated voltage to a functional unit, the current demand is determined, and a current control signal is generated. An off-SoC bulk current source accepts the current control signal and supplies auxiliary (bulk) current to the functional unit in response to the current control signal. For example, in a first period of time a dynamic increase demand for a first current. Initially the EVR supplies the first current and creates an increase in SoC thermal loading. Subsequently, the EVR supplies a current less than the first current while the bulk current source supplies the bulk of the current. As a result, the bulk current source creates an off-SoC thermal load.

Composite embedded voltage regulator (CEVR)

According to certain aspects, the invention allows a person to manage some of the functions of a cell phone without having to actually have the phone in her hands. For example, the invention allows the user to know of the incoming call and further allows the user to send a user-specified message to the caller and/or otherwise manage how the call should be handled through a remote device. In certain embodiments, the invention is comprised of: a decorative watch-like or bracelet-like case; a decorative wrist band; a vibrating incoming call indicator; a partial or full face display; touch screen input capability, accelerometer for wrist flick input capability, and/or side buttons for user inputs; a Bluetooth antenna; a Bluetooth transmitter and receiver; a rechargeable battery; a connector or wireless charging element; a display/general purpose control unit with firmware; and standard Bluetooth link and application software on an associated cellular phone.

Remote phone manager

Dynamic random access memory (DRAM) backchannel communication systems and methods are disclosed. In one aspect, a backchannel communication system allows a DRAM to communicate error correction information and refresh alert information to a System on a Chip (SoC), applications processor (AP), or other memory controller.

Dynamic random access memory (DRAM) backchannel communication systems and methods

Methods, apparatus, and system for use in adaptive communication interfaces are disclosed. An adaptive communication interface is provided, in which a high-speed clock provided in a high-speed mode of operation is suppressed in a low-power mode of operation. In the low-power mode of operation, a low-speed command clock is used for data transfers between a memory device and a system-on-chip, applications processor or other device. A method for operating the adaptive communication interface may include using a first clock signal to control transmissions of commands to a memory device over a command bus. In a first mode of operation, the first clock signal controls data transmissions over the adaptive communication interface. In a second mode of operation, the second clock signal controls data transmissions over the adaptive communication interface. The frequency of the second clock signal may be greater than the frequency of the first clock signal.

Low-power clocking for a high-speed memory interface

A CMOS device with a plurality of PMOS transistors each having a PMOS drain and a plurality of NMOS transistors each having an NMOS drain includes a first interconnect on an interconnect level extending in a length direction to connect the PMOS drains together. A second interconnect on the interconnect level extends in the length direction to connect the NMOS drains together. A set of interconnects on at least one additional interconnect level couple the first interconnect and the second interconnect together. A third interconnect on the interconnect level extends perpendicular to the length direction and is offset from the set of interconnects to connect the first interconnect and the second interconnect together.

Providing memory training of dynamic random access memory (DRAM) systems using port-to-port loopbacks, and related methods, systems, and apparatuses are disclosed. In one aspect, a first port within a DRAM system is coupled to a second port via a loopback connection. A signal is sent to the first port from a System-on-Chip (SoC), and passed to the second port through the loopback connection. The signal is then returned to the SoC, where it may be examined by a closed-loop engine of the SoC. A result corresponding to a hardware parameter may be recorded, and the process may be repeated until an optimal result for the hardware parameter is achieved at the closed-loop engine. By using a port-to-port loopback configuration, the DRAM system parameters regarding timing, power, and other parameters associated with the DRAM system may be trained more quickly and with lower boot memory usage.

Providing memory training of dynamic random access memory (DRAM) systems using port-to-port loopbacks, and related methods, systems, and apparatuses

Various aspects of an approach for routing die signals in an interior portion of a die using external interconnects are described herein. The approach provides for contacts coupled to circuits in the interior portion of the die, where the contacts are exposed to an exterior portion of the die. The external interconnects are configured to couple these contacts so that signals from the circuits in the interior portion of the die may be routed externally to the die. In various aspects of the disclosed approach, the external interconnects are protected by a packaging for the die.

Method and apparatus for routing die signals using external interconnects

A source-synchronous system is provided in which a non-uniform interface may exist in a data source endpoint as well as in a data sink endpoint.

Source-synchronous data transmission with non-uniform interface topology

Providing memory training of dynamic random access memory (DRAM) systems using port-to-port loopbacks, and related methods, systems, and apparatuses are disclosed. In one aspect, a first port within a DRAM system is coupled to a second port via a loopback connection. A training signal is sent to the first port from a System-on-Chip (SoC), and passed to the second port through the loopback connection. The training signal is then returned to the SoC, where it may be examined by a closed-loop training engine of the SoC. A training result corresponding to a hardware parameter may be recorded, and the process may be repeated until an optimal result for the hardware parameter is achieved at the closed-loop training engine. By using a port-to-port loopback configuration, the DRAM system parameters regarding timing, power, and other parameters associated with the DRAM system may be trained more quickly and with lower boot memory usage.

Growing community of inventors

Escondido, CA, United States of America

Michael J Brunolli