Intel Corporation

Micron Technology Incorporated

Other

Analog Devices,inc.

Advanced Micro Devices Corporation

Hewlett-Packard Development Company, L.p.

Mediatek Corporation

Arm Limited

Michael J Allen

Fangxing Wei

Dan Shi

Khushal Chandan

Jonathan H Liu

Charles H Lucas

Setul M Shah

Tyler J Gomm

Jose Fridman

Jeffrey L Miller

James W Conary

David P DiMarco

Terry L Baucom

Hebbalalu S Ramagopal

Stephen F Sullivan

Rajesh Sundaram

Shekoufeh Qawami

Stephen Anthony Fischer

Ravi P Singh

Marc M Hoffman

Richard D Pashley

Joern Soerensen

David R Gray

Joseph D Schutz

Patrick P Gelsinger

David J Shield

Babak Sabi

Stuart T Hopkins

Gregory K Crain

Mark I Gardner

H Jim Fulford

David B Witt

Charles P Roth

Lawrence A Booth

William C Anderson

Ravi Kolagotla

Kenneth C Duisenberg

James Dennis Dodrill

Palle Birk

Thomas Tomazin

Joseph Patrick Geisler

Ryo Inoue

Moinul Syed

Kenneth Nicholas Konesky

Bernard Deadman

Gary S Saunders

Gregory W Ledenbach

Jay J Seaton

Donald Landis

Patrick B Lee

Diana Esmail-Zandi

Lars Soendergaard Bertelsen

David Linzy

Joshua Kennon Crechriou

Susan B Luca

Gustay Laub, Iii

Gustav Laub, Iii

Tim Landreth

A processor is described that includes a plurality of compute units. One or more test pattern generators generates one or more test patterns and inputs the one or more test patterns into one or more of the plurality of compute units during testing, which testing includes processing of the one or more test patterns by one or more of the plurality of compute units. One or more control and sequencing logic units identifies an idle period during normal use of the processor in which a compute unit of the plurality of compute units is idle. The one or more control and sequencing units controls the test pattern generator to generate and input the one or more test patterns to the idle compute unit and controls the compute unit to process the one or more test patterns during the idle period. One or more comparators compares a result of testing with an expected result of testing to determine if the compute unit is functioning correctly.

Method of testing one or more compute units

Digital delay locked loop circuits, devices systems, and associated methods are provided and described. Such devices, systems, and methods utilize an open loop measurement for establishing a coarse delay lock.

Coarse delay lock estimation for digital DLL circuits

An electronic device including: a delay circuit configured to adjust a delay of an input for generating an output signal; and an input selection circuit coupled to the delay circuit, the input selection circuit configured to control a phase for a clock input based at least in part on a measurement of a delay corresponding to the delay circuit in generating the input.

Electronic device with a timing adjustment mechanism

A memory device performs DLL (delay locked loop) calibration in accordance with a DLL calibration mode configured for the memory device. A host controller can configure the calibration mode based on operating conditions for the memory device. The memory device includes an input/output (I/O) interface circuit and a delay locked loop (DLL) circuit coupled to control I/O timing of the I/O interface. A control circuit of the memory device selectively enables and disables DLL calibration in accordance with the DLL calibration mode. When selectively enabled, the DLL calibration is to operate at a time interval identified by the DLL calibration mode, and when selectively disabled, the DLL calibration is to cease or refrain from DLL calibration operations.

Flexible DLL (delay locked loop) calibration

Methods, systems, and devices for jitter cancellation with automatic performance adjustment are described. Within a clock distribution system in an electronic device (e.g., a memory device), a jitter cancellation system may be configured to introduce delay between an input clock signal and output clock signal that is directly proportional to the supply voltage for the clock distribution system. In response to supply noise, the delay introduced by the jitter cancellation system may vary directly with respect to the supply voltage fluctuations and thus may offset fluctuations in the delay introduced by other components of the clock distribution system, which may vary inversely with respect to the supply voltage fluctuations. A control component within the jitter cancellation system may execute an algorithm to adjust or regulate the delay introduced by the jitter cancellation system, including its responsiveness to fluctuations in the supply voltage.

Jitter cancellation with automatic performance adjustment

An electronic device including: a variable delay circuit configured to adjust a delay of a variable delay input for generating an output signal; a decision circuit coupled to the variable delay, the decision circuit configured to: generate a start signal for the variable delay circuit to begin measuring a coarse delay, generate a stop signal for the variable delay circuit to stop measuring the coarse delay, and generate an inversion-decision signal based at least in part on measuring the coarse delay; and an input selection circuit coupled to the variable delay circuit and the decision circuit, the input selection circuit configured to control a phase for a clock input based on the inversion-decision signal in generating the variable delay input.

Phase compensation in an I/O (input/output) circuit includes variable, programmable slope. A phase compensation circuit can apply phase compensation of one slope and dynamically change the slope of the phase compensation to allow for better tracking of environmental conditions. The phase compensation circuit can generate a linear code to apply phase compensation to lock phase of an I/O signal to a phase of a timing signal. The circuit selectively adjusts the linear code with a variable, programmable slope, where the slope defines how much phase compensation is applied per unit change in the linear code. The circuit applies the adjusted linear code to a lock loop to lock the phase of the I/O signal to the phase of the timing signal.

Digital phase control with programmable tracking slope having a programmable linear decoder using a coarse code and a fine code to generate delay adjustments to the phase of an input signal

Technology for a phase detector is described. The phase detector can include a reference clock. The phase detector can include a feedback clock. The phase detector can include a first latch operable to set a first latch output depending on a lead-lag status between the reference clock and the feedback clock. The phase detector can include a second latch that loads the lead-lag status when the reference clock and the feedback clock produce clock signals in a high state. The phase detector can include a third latch that loads the lead-lag status from the second latch when the reference clock and the feedback clock produce clock signals in a low state.

Phase detector in a delay locked loop

Examples may include techniques for dual-range clock duty cycle tuning of a clock signal used for an input/output data bus. A clock duty cycle of the clock signal is monitored to determine whether the clock duty cycle falls within a threshold of a 50 percent duty cycle. A dual-range tuning is then implemented until the clock duty cycle of the clock signal falls within the threshold.

Dual-range clock duty cycle corrector

Digital phase control with programmable tracking slope

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Rescue, CA, United States of America

Michael J Allen