Qlogic Corporation

Western Digital Technologies, Inc.

Michael Ivan Thompson

Derek J Rohde

Bruce Anthony Klemin

Joseph Harold Steinmetz

Murthy Kompella

Ying Ping Lok

Shashank Pandhare

Douglas Edwin O'Neil

Ronald M Mercer

David C Somayajulu

Martin Daniel Stainbrook

The current document is directed to a family of integrated hardware controllers that provides for cost-effective, high-bandwidth, and scalable incorporation of SSDs into large, distributed-computer systems. Certain implementations of the integrated hardware controller include dual media-access controllers for connection to one or more local area networks, remote-direct-memory-access ('RDMA') controllers for supporting RDMA protocols over the local area network, an NVMe controller that provides access to an SSD. In certain integrated-hardware-controller implementations, the RDMA and NVMe controllers are implemented in one of a field programmable gate array ('FPGA') and application-specific integrated circuit (&#x201c;ASIC&#x201d;).

Integrated network-attachable controller that interconnects a solid-state drive with a remote server computer

With CRC-code-computation logic used in electronic-communications hardware, many current implementations employ a number n of XOR matrices equal to the number of bytes in the fundamental data unit, or word, operated on by the CRC-code-computation logic. As the size, in bytes, of the fundamental-data-unit increases, due to increases in the widths of internal data-transmission components, the number n of XOR matrices in CRC-code-computation logic has correspondingly increased. A component-efficient CRC-code-computation logic employs message-padding logic in order to compute CRC codes using only a single XOR matrix. The message-padding logic takes advantage of certain characteristics of CRC codes to transform original input messages having lengths, in bytes, that are not evenly divisible by the length of the fundamental data unit into messages that are evenly divisible by the length of the fundamental data unit by prepending padding bytes to the original messages.

Component-efficient cyclic-redundancy-check-code-computation circuit

A method and system for transferring iSCSI protocol data units ('PDUs') to a host system is provided. The system includes a host bus adapter with a TCP/IP offload engine. The HBA includes, a direct memory access engine operationally coupled to a pool of small buffers and a pool of large buffers, wherein an incoming PDU size is compared to the size of a small buffer and if the PDU fits in the small buffer, then the PDU is placed in the small buffer. If the incoming PDU size is compared to a large buffer size and if the incoming PDU size is less than the large buffer size then the incoming PDU is placed in the large buffer. If the coming PDU size is greater than a large buffer, then the incoming PDU is placed is more than one large buffer and a pointer to a list of large buffers storing the incoming PDU is placed in a small buffer.

Method and system for efficiently using buffer space

A method for processing IP datagrams using an outbound processing state machine, in an outbound processor, wherein the IP datagrams are generated by a host system is provided. The method includes, creating an IOCB with plural host memory addresses that define host data to be sent and a host memory address of a network control block ('NCB') used to build network protocol headers, wherein the host sends the IOCB to the outbound processor. The outbound processor reads the NCB from host memory and creates an IP and MAC level protocol header(s) for a data packet(s) used to send the IP data. If a datagram fits into an IP packet, the outbound processor builds headers to send the datagram and then uses the plural host memory addresses defining the host data to read the data from the host, places the data into the packet and sends the packet.

Method and system for processing network data packets

A system with a host bus adapter ('HBA') having a TCP/IP offload engine is provided. The HBA includes logic for concurrently processing markers, data integrity fields ('DIFs') and digests by using plural counters that count words in a data stream and individual routing bits are set for markers, DIFs and digests based on the plural counter values. When a counter reaches a certain threshold value, then locator bits are set for a field and the locator bits are forwarded with the data stream. A marker counter is incremented when each word in a data stream passes by the marker counter and markers can be inserted at a programmed interval. For DIF calculation an offset of a first byte in a DMA transfer and partial cyclic redundancy code value is seeded into a DIF location counter, which is incremented for each byte of data that passes by the DIF location counter.

Method and system for processing markers, data integrity fields and digests

Method and system for receiving and sending network packets from a network is provided. The system includes, a host processor that executes an operating system for a host system and at least one application that runs in a context that is different from a context of the operating system; and a network adapter with a hardware device that can run a network protocol stack, wherein the application can access the network adapter directly via an application specific interface layer without using the operating system.

Dedicated application interface for network systems

A method and system for transferring iSCSI protocol data units ('PDUs') to a host system is provided. The HBA includes, a direct memory access engine operationally coupled to a pool of small buffers and a pool of large buffers, wherein an incoming PDU size is compared to the size of a small buffer and if the PDU fits in the small buffer, then the PDU is placed in the small buffer. The incoming PDU size is compared to a large buffer size and if the incoming PDU size is less than the large buffer size then the incoming PDU is placed in the large buffer. If the coming PDU size is greater than a large buffer, then the incoming PDU is placed is more than one large buffer and a pointer to a list of large buffers storing the incoming PDU is placed in a small buffer.

A method for processing IP datagrams using an outbound processing state machine in an outbound processor, wherein the IP datagrams are generated by a host system is provided. The method includes, creating an IOCB with plural host memory addresses that define host data to be sent and a host memory address of a network control block ('NCB') used to build network protocol headers, wherein the host sends the IOCB to the outbound processor. The outbound processor reads the NCB from host memory and creates an IP and MAC level protocol header(s) for a data packet(s) used to send the IP data. If a datagram fits into an IP packet, the outbound processor builds headers to send the datagram and then uses the plural host memory addresses defining the host data to read the data from the host, places the data into the packet and sends the packet.

Method and system for performing hardware tasks using a hardware state machine and a processor is provided. The method includes, setting a breakpoint for a state machine state; running the processor in a parallel mode with the state machine; passing control to the processor after a breakpoint condition is encountered; performing a task, wherein the processor performs the task which was meant to be performed by the state machine; and transferring control back to the state machine after the processor performs the task. The system includes an Application Specific Integrated Circuit (ASIC) with the state machine, and the processor.

Method and system for designing a flexible hardware state machine

A method for sending/receiving a TCP segment is provided. The sending process includes, determining if a TCP port can be offloaded; saving a host system's time stamp value; replacing a host system's time stamp value with a TCP offload engine ('TOE') adapter's time stamp value; and sending the TCP segment via the TOE adapter. The receiving process includes verifying if a TCP port is being offloaded by a host system to the TOE adpter; retrieving the host system's time stamp value; and inserting the host system's time stamp value in the received TCP segment before the forwarding the received TCP segment to the host system.

TCP time stamp processing in hardware based TCP offload

A system for transmitting and receiving TCP/IP data packets using a hardware engine is provided. The system includes an inbound MAC Receive state machine for processing MAC frames received from a network; an inbound IP verifier state machine for verifying IP packet headers; an inbound IP fragment processing state machine for processing and reassembling IP fragments; and an inbound TCP state machine for processing TCP segments received from an IP layer. The system also includes an outbound MAC Transmit state machine that sends MAC frames to a network; an outbound IP state machine that processes IP data to be passed to a MAC layer for transmission; and an outbound TCP state machine that processes TCP data to be passed to the IP layer for transmission.

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Colfax, CA, United States of America

Michael Ivan Thompson