Nvidia Corporation

Michael Ivan Halfen

Wen-Hung Lo

Jaewon Lee

Abhishek Dhir

Jiwang Lee

Po-Chien Chiang

Hsuche Nee

Chunjen Su

The differential voltage output from a first reference voltage generator of a multi-rank circuit is trained on multiple ranks of the multi-rank circuit. Multiple local reference voltage generators are trained to generate reference voltages for communication on the individual ranks, where the reference voltages output by the local reference voltage generators fall within a range of the differential voltage output.

Training and configuration of reference voltage generators in a multi-rank circuit system

A method includes generating a differential voltage from a first reference voltage generator; receiving the differential voltage at a second reference voltage generator; dividing the differential voltage at the second reference voltage generator into multiple available reference voltage levels; and selecting one of the available reference voltage levels to apply to a circuit.

Distributed global and local reference voltage generation

A multi-rank circuit system includes multiple transmitters each switchably coupled to a first end of a shared input/output (IO) channel and a unified receiver coupled to a second end of the shared IO channel. The unified receiver is coupled to apply a preconfigured analog reference voltage to set a differential output of the unified receiver, and further configured to apply a variable digital code to adjust the differential output according to a particular one of the transmitters that is switched to the shared IO channel.

Digitally controlled unified receiver for multi-rank system

A multi-rank system includes multiple circuit ranks communicating over a common data line to multiple data receivers, each corresponding to one or more of the ranks and each having a corresponding reference voltage generator and clock timing adjustment circuit, such that a rank to communicate on the shared data line is switched without reconfiguring outputs of either the reference voltage generators or the clock timing adjustment circuits.

Multi-rank receiver

A multi-rank circuit system utilizing a shared IO channel includes a first stage of multiple selectors coupled to input multiple digital busses, and a second stage including one or more selectors coupled to receive outputs of the first stage of selectors and to individually select one of the outputs of the first stage of selectors to one or more control circuits for IO circuits of the ranks. The system switches one of the ranks to be an active rank on the shared IO channel, and operates the first stage of selectors to select one of the digital busses to the second stage of selectors in advance of switching a next active rank to the shared IO channel.

Look ahead switching circuit for a multi-rank system

Improved methods and systems for accessing a memory in a computer are disclosed. In one embodiment, the true and complement portions of a differential write clock signal are employed as two single ended clock signals for independently controlling different memory chips in a memory system. For example, in a memory system having two memory chips, one memory chip is configured to use the true write clock signal and the other memory chip is configured to use the complement write clock signal. Employing the differential write clock signal as two single ended clock signals allows overlapping of write and read operations across multiple memory chips, reducing the time needed for accessing memory. Accordingly, the disclosed methods and systems provide a more efficient memory system that can be used to improve the operation of a computer.

Growing community of inventors

San Francisco, CA, United States of America

Michael Ivan Halfen