International Business Machines Corporation

Microsoft Technology Licensing, LLC

Michael Ignatowski

Thomas James Heller, Jr

James Walter Rymarczyk

Noshir Cavas Wadia

Kerry Bernstein

Philip George Emma

Bernard S Meyerson

Luis Alfonso Lastras-Montano

Wayne Frederick Ellis

Peter Anthony Franaszek

Howard L Kalter

Stanley Everett Schuster

David Meltzer

William Todd Boyd

Michael Raymond Trombley

David Michael Daly

Richard Edward Matick

Jeffrey H Dreibelbis

Richard I Baum

Lishing Liu

Matthew A Krygowski

Gregory Salyer

Peng Ye

Donald W Price

Patrick M Gannon

Yee-Ming Ting

William K Rodiger

Gottfried Andreas Goldiran

Michael P Witt

A multiple-core processor supporting multiple instruction set architectures provides a power-efficient and flexible platform for virtual machine environments requiring multiple support for multiple instruction set architectures (ISAs). The processor includes multiple cores having disparate native ISAs and that may be selectively enabled for operation, so that power is conserved when support for a particular ISA is not required of the processor. The multiple cores may share a common first level cache and be mutually-exclusively selected for operation, or multiple level-one caches may be provided, one associated with each of the cores and the cores operated as needed, including simultaneous execution of disparate ISAs. A hypervisor controls operation of the cores and locates a core and enables it if necessary when a request to instantiate a virtual machine having a specified ISA is received.

Multiple-core processor supporting multiple instruction set architectures

A stacked semiconductor chip comprising multiple unit chips contains multiple instances of a first chip component that have a low yield and are distributed among the multiple unit chips. An instance of the first chip component within a first unit chip is logically paired with at least another instance of the first chip component within at least another unit chip so that the combination of the multiple instances of the first chip component across the multiple unit chips constitute a functional block providing the functionality of a fully functional instance of the first chip component. The stacked semiconductor chip may include multiple instances of a second chip component having a high yield and distributed across the multiple unit chips. Multiple low yield components constitute a functional block providing an enhanced overall yield, while high yield components are utilized to their full potential functionality.

Semiconductor chip stacking for redundancy and yield improvement

Computer memory management systems and methods are provided in which data block buffering and priority scheduling protocols are utilized in compressed memory systems to mask the latency associated with memory reorganization work following access to compressed main memory. In particular, data block buffers and priority scheduling protocols are implemented to delay and prioritize memory reorganization work to allow resources to be used for serving new memory access requests and other high priority commands.

Systems and methods for masking latency of memory reorganization work in a compressed memory system

Multiple instruction set architectures are supported in a system that provides a power-efficient and flexible platform for virtual machine environments requiring multiple support for multiple instruction set architectures (ISAs). A processor includes multiple cores having disparate native ISAs and that may be selectively enabled for operation, so that power is conserved when support for a particular ISA is not required of the processor. A hypervisor controls operation of the cores, locates a core and enables it if necessary when a request to instantiate a virtual machine having a specified ISA is received. The ISA may be specified by a particular operating system and/or application program requirements.

An apparatus is provided for modeling queuing systems with highly variable traffic arrival rates. The apparatus includes means to associate a value with a pattern of highly variable arrival rates that is simple and intuitive, and a means to accurately model queuing delays in systems that are characterized by bursts of arrival activity. The queuing delay is determined by a sum of queuing delays after first applying a weighting factor to the queuing delay based upon a random arrival rate, and a different weighting factor to the queuing delay based upon a bursty variable arrival rate. The weighting factors are variants of the server utilization. The model facilitates specification of server characteristics and configurations to meet response time metrics.

Apparatus for modeling queueing systems with highly variable traffic arrival rates

A method, system, and computer program product are disclosed for dynamically managing power in a microprocessor chip that includes physical hardware elements within the microprocessor chip. A process is selected to be executed. Hardware elements that are necessary to execute the process are then identified. The power in the microprocessor chip is dynamically altered by altering a present power state of the hardware elements that were identified as being necessary.

System and computer program product for dynamically managing power in microprocessor chips according to present processing demands

A multiprocessor computer system has a plurality of processing nodes which use processor state information to determine which coherent caches in the system are required to examine a coherency transaction produced by a single originating processor's storage request. A node of the computer has dynamic coherency boundaries such that the hardware uses only a subset of the total processors in a large system for a single workload at any specific point in time and can optimize the cache coherency as the supervisor software or firmware expands and contracts the number of processors which are being used to run any single workload. Multiple instances of a node can be connected with a second level controller to create a large multiprocessor system. The node controller uses the mode bits to determine which processors must receive any given transaction that is received by the node controller. The second level controller uses the mode bits to determine which nodes must receive any given transaction that is received by the second level controller. Logical partitions are mapped to allowable physical processors. Cache coherence regions which encompass subsets of the total number of processors and caches in the system are chosen for their physical proximity. A distinct cache coherency region can be defined for each partition using a a hypervisor.

Multiprocessor system with dynamic cache coherency regions

Method for dynamically managing power in microprocessor chips according to present processing demands

A method are provided for modeling queuing systems with highly variable traffic arrival rates. The method includes a means to associate a value with a pattern of highly variable arrival rates that is simple and intuitive, and a means to accurately model queuing delays in systems that are characterized by bursts of arrival activity. The queuing delay is determined by a sum of queuing delays after first applying a weighting factor to the queuing delay based upon a random arrival rate, and a different weighting factor to the queuing delay based upon a bursty variable arrival rate. The weighting factors are variants of the server utilization. The model facilitates specification of server characteristics and configurations to meet response time metrics.

Apparatus and method for modeling queueing systems with highly variable traffic arrival rates

The present invention discloses a method, system and article of manufacture for performing analytic modeling on a computer system by handling a plurality of predefined system criteria directed to a modeled computer system. The present invention provides means for the user of an analytic model to specify (i.e. enable) any number of predefined system criteria that must all be simultaneously satisfied. The modeling methodology uses a variation of the well-known Mean Value Analysis technique in its calculations. Response times, resource utilizations, and resource queue lengths are initially estimated for a small user arrival rate. An iterative method is used to gradually increase the user arrival rate by a constant value. For each iteration, response times, resource utilizations, and resource queue lengths are calculated. Then for all the criteria, which have been enabled, it is checked to see if the value limits specified for those criteria have exceeded. If not, the model calculation results are saved and next iteration is started. The model iterations continue with a gradually increasing user arrival rate until one or more of the modeling criteria are exceeded. At that time the model outputs the results from the previous iteration (i.e. the saved results where all the criteria were still satisfied), and the modeling calculations are finished. The model results may be used as input for further processing.

Method, system and article of manufacture for an analytic modeling technique for handling multiple objectives

A method, system and article of manufacture for estimating the performance of a computer system are provided. Initially, a business pattern representative of the expected usage of the computer system is identified. Then, for each parameter associated with each predefined script, which corresponds to the identified business pattern, a value is established. The computer system hardware characteristics and performance objectives are identified next. The performance estimate is then calculated utilizing the established parameter values, identified hardware characteristics and performance objectives. To calculate the performance estimate, the script measurements data is read from a table of previously measured values, and a weighted average number of page visits per user, a weighted average visit rate and a weighted average service time for each target device in the computer system are calculated. A total response time and a system throughput are calculated by varying each target device queue length and user arrival rate until the performance objectives are reached.

Method and system of an integrated simulation tool using business patterns and scripts

A novel structure for a highly-scaleable high-performance shared-memory computer system having simplified manufacturability. The computer system contains a repetition of system cells, in which each cell is comprised of a processor chip and a memory subset (having memory chips such as DRAMs or SRAMs) connected to the processor chip by a local memory bus. A unique type of intra-nodal busing connects each system cell in each node to each other cell in the same node. The memory subsets in the different cells need not have equal sizes, and the different nodes need not have the same number of cells. Each node has a nodal cache, a nodal directory and nodal electronic switches to manage all transfers and data coherence among all cells in the same node and in different nodes. The collection of all memory subsets in the computer system comprises the system shared memory, in which data stored in any memory subset is accessible to the processors on the other processor chips in the system. Each location in the system shared memory has a unique real address, which may be used by any processor in the system. Thus, the same memory addresses may be used in the executable instructions of all processors in the system. The nodal directories automatically manage the coherence of all data being changed in all processor caches in the computer system, regardless of where the data is stored in the shared memory of the system and regardless of which cell in the system contains the processor changing the data to provide data coherence across all nodes in the computer system.

Scaleable shared-memory multi-processor computer system having repetitive chip structure with efficient busing and coherence controls

An integrated processor and level two (L2) dynamic random access memory (DRAM) are fabricated on a single chip. As an extension of this basic structure, the invention also contemplates multiprocessor 'node' chips in which multiple processors are integrated on a single chip with L2 cache. By integrating the processor and L2 DRAM cache on a single chip, high on-chip bandwidth, reduced latency and higher performance are achieved. A multiprocessor system can be realized in which a plurality of processors with integrated L2 DRAM cache are connected in a loosely coupled multiprocessor system. Alternatively, the single chip technology can be used to implement a plurality of processors integrated on a single chip with an L2 DRAM cache which may be either private or shared. This approach overcomes a number of issues which limit the performance and cost of a memory hierarchy. When the L2 DRAM cache is placed on the same chip as the processor, the time needed for two chip-to-chip crossings is eliminated. Since these crossings require off-chip drivers and receivers and must be synchronized with the system clock, the time involved is substantial. This means that with the integrated L2 DRAM cache, latency is reduced.

Integrated processing and L2 DRAM cache

Provides within a semiconductor chip a plurality of internal DRAM arrays connected to each section data bus. A cross-point switch simultaneously connects the plural section data buses to a corresponding plurality of port registers that transfer data between a plurality of ports (I/O pins) on the chip and the section data buses in parallel in either data direction to effectively support a high multi-port data rate to/from the memory chip. For any section, the data may be transferred entirely in parallel between the associated port and a corresponding port register, or the data may be multiplexed between each port and its port register in plural sets of parallel bits. Each of the DRAM banks in the chip is addressed and accessed in parallel with the other DRAM banks through a bank address control in the chip which receives all address requests from four processors in a computer system. Each section data bus is comprised of a large number of data lines that transfer data bits in parallel to/from all of DRAM cells in an address-selected row in one of the DRAM banks at a time in each section. The four DRAM section buses in the chip may be transferring data at the same time in independent directions to/from the four chip ports.

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Michael Ignatowski