Intel Corporation

Fulcrum Microsystems, Inc.

Fulcrum Microystems Inc.

Michael I Davies

Andrew M Lines

Robert G Southworth

Uri V Cummings

Peter A Beerel

Zhi-Hern Loh

Tsung-Han Lin

Jonathan Tse

A neuromorphic computing apparatus has a network of neuromorphic cores, with each core including an input axon and a plurality of neurons having synapses. The input axon is associated with an input data store to store an input trace representing a time series of filtered pre-synaptic spike events, and accessible by the synapses of the plurality of neurons of the core. Each neuron includes at least one dendritic compartment to store and process variables representing a dynamic state of the neuron. Each compartment is associated with a compartment-specific data store to store an output trace representing a time series of filtered post-synaptic spike events. Each neuron includes a learning engine to apply a set of one or more learning rules based on the pre-synaptic and post-synaptic spike events to produce an adjustment of parameters of a corresponding synapse to those spike events.

Trace-based neuromorphic architecture for advanced learning

System and techniques for variable epoch spike train filtering are described herein. A spike trace storage may be initiated for an epoch. Here, the spike trace storage is included in a neural unit of neuromorphic hardware. Multiple spikes may be received at the neural unit during the epoch. The spike trace storage may be incremented for each of the multiple spikes to produce a count of received spikes. An epoch learning event may be obtained and a spike trace may be produced in response to the epoch learning event using the count of received spikes in the spike trace storage. Network parameters of the neural unit may be modified using the spike trace.

Variable epoch spike train filtering

An electronic neuromorphic core processor circuit and related method include a dendrite circuit comprising an input that receives an input spike message having an associated input identifier that identifies a distribution set of dendrite compartments. A synapse map provides a mapping of the received identifier to a synapse configuration in the memory. A synapse configuration circuit associates the identifier with a set of synaptic connections, possibly shared hierarchically over populations of neurons defined implicitly by the mapping structures, that are read from the memory. The synaptic connections determine n-tuple information comprising a dendrite ID, a weight, and a network delay time. A dendrite accumulator circuit accumulates weight values scheduled at the appropriate future time as identified by the n-tuple information and maps them to a soma compartment. A soma circuit maintains a soma compartment state in response to the accumulated weight values scheduled for servicing and, when sufficiently activated, produces output spikes.

Population-based connectivity architecture for spiking neural networks

An electronic neuromorphic core processor circuit and related method include a processor, an electronic memory, and a dendrite circuit comprising an input circuit that receives an input spike message having an associated input identifier that identifies a distribution set of dendrite compartments. A synapse map table provides a mapping of the received identifier to a synapse configuration in the memory. A synapse configuration circuit comprises a routing list that is a set of synaptic connections related to the set of dendrite compartments, each being n-tuple information comprising a dendriteID and a weight stored in the memory. The synapse configuration circuit associates the identifier with the set of synaptic connections, a dendrite accumulator comprising a weighting array. It accumulates weight values within a dendritic compartment identified by the dendriteID and based on the n-tuple information associated with the set of synaptic connections associated with the identifier.

Scalable neuromorphic core with shared synaptic memory and variable precision synaptic memory

Systems and methods may include neuromorphic traffic control, such as between cores on a chip or between cores on different chips. The neuromorphic traffic control may include a plurality of routers organized in a mesh to transfer messages; and a plurality of neuron cores connected to the plurality of routers, the neuron cores in the plurality of neuron cores to advance in discrete time-steps, send spike messages to other neuron cores in the plurality of neuron cores during a time-step, and send barrier messages.

Neuromorphic core and chip traffic control

Highly configurable frame processing pipelines are enabled in packet switches in an efficient manner which satisfies stringent area and power requirements. Frame processing pipelines are described that enable dynamic processing of different types of frames on a per frame basis.

Configurable frame processing pipeline in a packet switch

A shared memory switch and switch fabric architecture are described which employ partitions of the shared memory to implement multiple, independent virtual congestion domains, thereby allowing congestion to be handled for different classes of traffic independently.

Flow and congestion control in switch architectures for multi-hop, memory efficient fabrics

Methods and apparatus are described for optimizing a circuit design. A gate level circuit description corresponding to the circuit design is generated. The gate level circuit description includes a plurality of pipelines across a plurality of levels. Using a linear programming technique, a minimal number of buffers is added to selected ones of the pipelines such that a performance constraint is satisfied.

Logic synthesis of multi-level domino asynchronous pipelines

Methods and apparatus are described for assigning data units to a plurality of groups. A key is generated for each of the data units such that the keys corresponding to associated ones of the data units are identical. An initial hash value is generated for each of the keys. A number of techniques are described for then deterministically scrambling the initial hash values such that small bit changes in the keys will typically produce stochastically large changes in the final hash values. The data units are mapped to specific ones of the groups with reference to the scrambled hash values.

Traffic distribution techniques utilizing initial and scrambled hash values

An interface for use between an asynchronous domain and a synchronous domain is described. The asynchronous domain is characterized by transmission of data in accordance with a delay-insensitive handshake protocol. The synchronous domain is characterized by transmission of data in accordance with transitions of a clock signal. The interface includes a datapath operable to transfer a data token between the domains. The interface also includes control circuitry operable to enable transfer of the data token via the datapath in response to a transition of the clock signal and at least one completion of the handshake protocol.

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Portland, OR, United States of America

Michael I Davies