Silicon Genesis Corporation

Other

Ahbee 1, L.p.

Michael I Current

Theodore E Fong

Vladimir Faifer

Timothy Wong

Thomas E Seidel

Igor J Malik

Sien G Kang

Phuc Van

Harry Robert Kirk

Philip James Ong

Ariel Flat

Martin Fuerfanger

Implanting ions to form a cleave layer in a semiconductor device causes damage to sensitive materials such as high-K dielectrics. In a process for forming a cleave layer and repairing damage caused by ion implantation, ions are implanted through a circuit layer of a substrate to form a cleave plane. The substrate is exposed to a hydrogen gas mixture for a first time at a first temperature to repair damage caused by the implanted ions. A cleaving process may then be performed, and the cleaved substrate may be stacked in a 3DIC structure.

Method of forming semiconductor device using high stress cleave plane

Forming a 3DIC includes providing a lower device structure comprising a first substrate with a circuit layer, providing an interconnect network layer having an interconnect structure with a first coupled to a second plurality of electrodes by connection structures on a semiconductor substrate, the first plurality of electrodes being exposed on a first surface of the interconnect layer, implanting ions through the interconnect structure to form a cleave plane in the semiconductor substrate, bonding the interconnect structure to the lower device structure so that electrodes of the first plurality of electrodes are coupled to corresponding electrodes on the lower device structure, cleaving the substrate of the bonded interconnect layer at the cleave plane, removing material from the semiconductor substrate until the second plurality of electrodes is exposed, and bonding an upper device layer to the interconnect structure.

Three dimensional integrated circuit with lateral connection layer

A method of forming a semiconductor device includes providing a semiconductor substrate with a circuit layer, forming a range compensating layer over the semiconductor substrate, the range compensating layer having a plurality of different thicknesses, each of the plurality of different thicknesses being inversely proportional to a stopping power of structures disposed under the respective thickness of the range compensating layer, implanting ions into the semiconductor substrate, the ions traveling through the range compensating layer and the circuit layer to define a cleave plane in the semiconductor substrate, removing the range compensating layer, and cleaving the semiconductor substrate at the cleave plane. The range compensating layer can be used to compensate for variations in ion penetration depth.

Method of forming semiconductor device using range compensating material

Processes for the localized etching of films on the sidewalls of non-planar 3D features such as a trench or a FinFET array. The etch process has a first step of an angle-directed ion implant beam, with the beam being self-aligned onto a localized region on a sidewall feature, that functionalizes the region for a second step that etches the ion implanted region.

Limited dose and angle directed beam assisted ALE and ALD processes for localized coatings on non-planar surfaces

Three dimensional integrated circuit

Processes for localized film deposition on semiconductor device surfaces having non-planar features. The processes use combinations of Limited-Dose Atomic Layer Etch, Limited Dose Atomic Layer Deposition, and Atomic Layer Deposition to provide localized coatings only near or on the bottom, or only near the center, or only near or on the top and bottom of trench and Fin features.

Limited dose atomic layer processes for localizing coatings on non-planar surfaces

A method of forming a device includes providing a first substrate having a first area and a second area, forming a range compensating material over the first substrate so that the first material is disposed over the first area and not disposed over the second area, implanting ions into the first area and the second area to form first and second cleave planes at first and second depths, respectively, each of the first and second cleave planes being defined by a concentration of the implanted ions, removing the range compensating material, and cleaving the first substrate along a cleave profile including the first and second cleave planes.

A stacked semiconductor device is formed by implanting ions through dielectric and conductive structures of a first substrate to define a cleave plane in the first substrate, cleaving the first substrate at the cleave plane to obtain a cleaved layer including the dielectric and conductive structures, bonding at least one die to the first substrate, the at least one die having a smaller width than a width of the first substrate, depositing a planarization material over the at least one die, planarizing the planarization material to form a planarized upper surface over the at least one die, and stacking a third substrate on the planarized upper surface.

A method comprises providing a first substrate having dielectric structures and conductive structures. Ions are implanted into the first substrate, the ions traveling through the dielectric structures and the conductive structures to define a cleave plane in the first substrate. The first substrate is cleaved at the cleave plane to obtain a cleaved layer having the dielectric structure and the conductive structures. The cleaved layer is used to form a three-dimensional integrated circuit device having a plurality of stacked integrated circuit (IC) layers, the cleaved layer being one of the stacked IC layers.

The present invention provides for treating a surface of a semiconductor material. The method comprises exposing the surface of the semiconductor material to a halogen etchant in a hydrogen environment at an elevated temperature. The method controls the surface roughness of the semiconductor material. The method also has the unexpected benefit of reducing dislocations in the semiconductor material.

Non-contact etch annealing of strained layers

A non-contact apparatus and method for measuring of the leakage current and capacitance of p-n junctions in test structures within scribe lanes of IC product wafers is disclosed. The apparatus comprises of a light source optically coupled with a fiber to a transparent electrode at the end of the fiber, which is brought close to the p-n junction under test. The ac signal generated from the test p-n junction is captured by this transparent and conducting coating electrode. The leakage current of a test p-n junction is determined using the frequency dependence of junction photo-voltage signal and reference signals from a p-n junction with low leakage current and known capacitance.

Non-contact method and apparatus for measurement of leakage current of p-n junctions in IC product wafers

A non-contact apparatus and method for measuring of the leakage current and capacitance of p-n junctions in test structures within scribe lanes of IC product wafers is disclosed. The apparatus has a light source optically coupled with a fiber to a transparent electrode at the end of the fiber, which is brought close to the p-n junction under test. The ac signal generated from the test p-n junction is captured by this transparent and conducting coating electrode. The leakage current of a test p-n junction is determined using the frequency dependence of junction photo-voltage signal and reference signals from a p-n junction with low leakage current and known capacitance.

A contactless sheet resistance measurement apparatus and method for measuring the sheet resistance of a surface p-n junction and its leakage current is disclosed. The apparatus comprises an alternating light source optically coupled with a transparent and conducting electrode brought close to the junction, a second electrode placed outside of the illumination area, and a third grounded electrode surrounding the first and second electrodes. For measurements of junction capacitance, a calibration wafer with known sheet resistance is used to provide reference photovoltage signals. Using the measurement of the junction photovoltage (JPV) signals from the illuminated area and outside this area for calibration and test wafers at different light modulation frequencies, p-n junction sheet resistance and conductance (leakage current density) are determined.

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San Jose, CA, United States of America

Michael I Current