Qualcomm Incorporated

Qualcomm Mems Technologies, Inc.

Michael Hugh Anderson

Chun Yu

Ann Chris Irvine

Dan MingLun Chuang

Geoffrey Shippee

Rajat Rajinderkumar Dhawan

Gunjan Upadhyay

Apparatus and method are described for trimming parameters of analog circuits. The apparatus includes trim result registers for storing trim results for adjusting parameters of analog circuits, respectively; a memory device configured to store sets of operands; and a trim calculation unit configured to generate the set of trim results by performing a set of arithmetic operations on the sets of operands based on a set of commands, respectively. The trim calculation unit receives a set of commands; transfers sets of operands from the memory device to a programmable ALU array based on the set of commands, respectively; generates trim results by performing arithmetic operations on the sets of operands based on the set of commands, respectively; and sends the trim results to the trim result registers based on the set of commands, respectively.

Apparatus and method for trimming parameters of analog circuits including centralized programmable ALU array

A 3D graphics pipeline includes a prefetch mechanism that feeds a cache of depth tiles. The prefetch mechanism may be predictive, using triangle geometry information from previous pipeline stages to pre-charge the cache, thereby allowing for an increase in memory bandwidth efficiency. A z-value compression technique may be optionally utilized to allow for a further reduction in power consumption and memory bandwidth.

Tiled prefetched and cached depth buffer

By locating the depth buffer of a 3D graphics rasterization pipeline in a dedicated high speed memory, bandwidth on a main bus can be eliminated that would otherwise result from hidden surface removal (HSR) hardware contained in the pipeline. Also, by reordering of read and write access commands to the depth buffer memory, it is possible to improve memory access throughput otherwise impacted by an increased latency of a read access.

Depth buffer for rasterization pipeline

A display device performs the fractional part of gamma translation by using a logarithm lookup table. The logarithm of an image data value is found in a look-up table. The retrieved result is multiplied by the fractional portion of the power, and a search in the look up table for this product produces an index related to the desired result. In another embodiment, rather than a search of the first look up table, a second inverse logarithm look up table is used to produce the desired result by looking up the exponentiation of the product.

Arbitrary power function using logarithm lookup table

This patent discloses a system and method to compile a set of display points that define a two dimensional representation of a straight line graphic object using three dimensional rasterization algorithms. In one embodiment, a three dimensional (3D) graphics accelerator may receive data. The data may define three vertices (x, y, K), (x, y, K), and (x, y, K) of a triangle primitive. Attributes K=(K+K)/2 and coordinates (x, y), (x, y), and (x, y) form an isosceles triangle primitive. Coordinates (x, y) and (x, y) define a base of the isosceles triangle primitive. The isosceles triangle primitive may be rendered using the three dimensional rasterization algorithms to obtain the set of display points that define a two dimensional representation of the base of the isosceles triangle primitive.

2D/3D line rendering using 3D rasterization algorithms

A three-dimensional (3D) graphics pipeline renders a sequence of images of 3D scenes each composed of a plural set of objects. The pipeline comprises an antialiasing oversampling mechanism to perform for a given image, at an early stage of the pipeline, oversampling on a portion of the objects of the given image.

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Levcadis, CA, United States of America

Michael Hugh Anderson