International Business Machines Corporation

University of Rochester

Huawei Technologies Co., Limited

Michael Huang

Harold Wade Cain, Iii

Jose Eduardo Moreira

Kattamuri Ekanadham

Mauricio J Serrano

David Michael Daly

Zeljko Ignjatovic

Swetha S George

Tongtong Cao

Swetha George

An ultrasound imaging system includes an array of ultrasound transducer elements chat send ultrasound energy into an object when energized for respective transmission time periods and provide responses to ultrasound energy emitted from the object for respective reception time periods, a reception modulation circuit modulating the responses with irregular sequences of modulation coefficients, a combiner circuit combining the modulated responses, and an image reconstruction processor configured to computer-process the combined modulated responses into one or more images of the object.

Ultrasound system for high-speed and high resolution imaging applications

A cache directory processing method for a multi-core processor system, and directory controllers is presented. The method includes obtaining a first directory entry corresponding to first-type storage space in shared storage space of the multi-core processor system and in a directory of the shared storage space; performing a directory entry combination operation on the first directory entry according to each directory entry in the first directory entry and according to an access type and a sharer, to form a second directory entry of the first-type storage space; and when a record quantity of the second directory entry is less than a record quantity of the first directory entry, replacing the first directory entry with the second directory entry, and using the second directory entry as a directory entry corresponding to the first-type storage space and in the directory of the shared storage space.

Cache directory processing method for multi-core processor system, and directory controller

A method for detecting a software-race condition in a program includes copying a state of a transaction of the program from a first core of a multi-core processor to at least one additional core of the multi-core processor, running the transaction, redundantly, on the first core and the at least one additional core given the state, outputting a result of the first core and the at least one additional core, and detecting a difference in the results between the first core and the at least one additional core, wherein the difference indicates the software-race condition.

Redundant transactions for detection of timing sensitive errors

A method for detecting errors in hardware including running a transaction on a plurality of cores, wherein each of the cores runs a respective copy of the transaction, periodically synchronizing the transaction on the cores throughout execution of the transaction, comparing results of the transaction on the cores, and determining an error in one or more of the cores.

Detection of hardware errors using periodically synchronized redundant transactions and comparing results from cores of a multi-core processor

A method for detecting errors in hardware including running a transaction on a plurality of cores, wherein each of the cores runs a respective copy of the transaction, synchronizing the transaction on the cores, comparing results of the transaction on the cores, and determining an error in one or more of the cores.

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Rochester, NY, United States of America

Michael Huang