Silicon Laboratories Inc.

Invensense, Inc.

Sitime Corporation

Texas Instruments Corporation

Massachusetts Institute of Technology

Invensease, Inc.

Michael Henderson Perrott

James Christian Salvia

Bruno Werner Garlepp

Yunteng Huang

Rex T Baird

Nikhil Apte

Bichoy Bahr

Shungneng Lee

Yang Pan

Julius Ming-Lin Tsai

Eldwin Ng

Marian Voros

Baher S Haroun

Michael Julian Daneman

Jerrell P Hein

Hao-Yen Tang

Douglas F Pastorello

Ting-Ta Yen

Igor Mucha

Etienne De Foras

Alireza Shirvani

Philip David Steiner

Swaminathan Sankaran

William Kerry Keal

Anantha P Chandrakasan

Franz Xaver Kaertner

Amaresh Virupanagouda Malipatil

Vadim Gutnik

Sriraman Dakshinamurthy

Fang Liu

Srisai Rao Seethamraju

Charles G Sodini

Timothy A Monk

Eric T King

Louis J Nervegna

Andy Milota

Robert Karl Butler

Matthew Z Straayer

Jeronimo Segovia-fernandez

Zhineng Zhu

Jung Won Kim

Scott Edward Meninger

Hon Kin Chiu

Zachary Schaffer

Jim Salvia

Fan Liu

In one example, an apparatus includes a MM divider having a clock input, a first divisor input and a MM divider output; a delta-sigma modulator having a second divisor input, a divisor output and a residual output, the divisor output coupled to the first divisor input; a DTC having a clock input, a control input, a calibration input, and an output, the DTC control input coupled to the residual output, and the DTC clock input coupled to the MM divider output; and a calibration circuit having a first calibration control input, a second calibration control input, and a calibration output, the first calibration control input coupled to the DTC output, the second calibration control input coupled to the residual output, and the calibration output coupled to the DTC calibration input.

Digital-to-time converter calibration

Exemplary multipath digital microphone described herein can comprise exemplary embodiments of adaptive ADC range multipath digital microphones, which allow low power to be achieved for amplifiers or gain stages, as well as for exemplary adaptive ADCs in exemplary multipath digital microphone arrangements described herein, while still providing a high DR digital microphone systems. Further non-limiting embodiments can comprise an exemplary glitch removal component configured to minimize audible artifacts associated with the change in the gain of the exemplary adaptive ADCs.

Adaptive analog to digital converter (ADC) multipath digital microphones

An oscillator circuit includes a first BAW oscillator, a first coupling stage, a second BAW oscillator, and a second coupling stage. The first BAW oscillator is configured to generate a first output signal at a frequency. The first coupling stage is coupled to the first BAW oscillator, and is configured to amplify the first output signal. The second BAW oscillator is coupled to the first coupling stage, and is configured to generate a second output signal at the frequency. The second output signal differs in phase from the first output signal. The second coupling stage is coupled to the first BAW oscillator and the second BAW oscillator, and is configured to amplify the second output signal and drive the first BAW oscillator.

Multi-phase oscillators

In some examples, an apparatus includes a delay-based frequency multiplier and an error detection circuit. The delay-based frequency multiplier has a clock input, a multiplier clock output, and a delay calibration input. The error detection circuit has a detection input and a detection output. The detection input is coupled to the multiplier clock output, and the detection output is coupled to the delay calibration input. The error detection circuit is configured to receive a clock signal at the detection input, and provide a period error signal at the detection output based on a time difference between a first edge of the clock signal and a second edge of a delayed version of the clock signal.

Frequency multiplier calibration

A tunable bulk acoustic wave (BAW) resonator includes: a first electrode adapted to be coupled to an oscillator circuit; a second electrode adapted to be coupled to the oscillator circuit; and a piezoelectric layer between the first electrode and the second electrode; and a Bragg mirror. The Bragg mirror has: a metal layer; and a dielectric layer between the metal layer and either of the first electrode or the second electrode. The tunable BAW resonator also includes: a radio-frequency (RF) signal source having a first end and a second end, the first end coupled to the first electrode, and the second end coupled to the second electrode; and an amplifier circuit between either the first electrode or the second electrode and the Bragg mirror metal layer.

Tunable bulk acoustic wave (BAW) resonator based on application of radio-frequency (RF) signal to Bragg mirror metal layer

A system comprises a digital processing circuit, a frequency modulator, an amplitude modulator, and an adder. The digital processing circuit receives an input signal and a correlation signal and generates a frequency tuning parameter and an amplitude modulation parameter. The frequency modulator generates a frequency modulation signal and the correlation signal. The amplitude modulator receives the amplitude modulation parameter and generates an amplitude modulation signal. The adder receives the frequency tuning parameter and the frequency modulation signal and generates a control signal. In some implementations, the system further comprises a DC feedback circuit that receives the input signal and generates a DC compensation signal. In some implementations, the system further comprises a temperature sensor, a temperature compensation circuit, and a second adder.

Methods and systems for atomic clocks with high accuracy and low Allan deviation

An audio activity detector device is disclosed. The audio activity detector device comprises a closed loop feedback regulating circuit that supplies an input signal representative of a time-varying voltage signal to a quantizer circuit, wherein the quantizer circuit, as a function of the input signal, converts the input signal to a quantizer discrete-time signal; a first circuit that, as a function of the discrete-time signal, determines a key quantizer statistic value for the quantizer discrete-time signal; and a second circuit that, as a function of the key quantizer statistic value, determines a signal statistic value for the input signal and a gain control value.

Low power always-on microphone using power reduction techniques

In described examples, a feedback loop has phase detection (PD) circuitry that has a reference input to receive a reference frequency signal, a feedback input to receive a feedback signal, and phase difference outputs. A phase to digital converter (P2DC) includes a first phase to charge converter (PCC) that has a gain polarity and a first phase error output; a second PCC that has an opposite gain polarity and a second phase error output. A differential loop filter has an amplifier with an inverting input coupled to the first phase error output and a non-inverting input coupled to the second phase error output. An analog to digital converter (ADC) has an input coupled to an output of the differential loop filter. A feedback path is coupled to the output of the P2DC, with an output of the feedback path providing the feedback signal to the PD feedback input.

High gain detector techniques for low bandwidth low noise phase-locked loops

In described examples, a phase locked loop (PLL) has a first phase detector cell (PD) that has a gain polarity. The first PD cell has a phase error output and inputs coupled to a reference frequency signal and a feedback signal. A second PD cell has an opposite gain polarity. The second PD cell has a phase error output and inputs coupled to the reference frequency signal and the feedback signal. A loop filter has a feedforward path and a (lossy) integrating path coupled to an output of the filter. The feedforward path has a third PD cell that has phase error output AC-coupled to the filter output. The integrating path includes an opamp that has an inverting input coupled to the first PD cell phase error output and a non-inverting input coupled to the second PD cell phase error output.

High gain detector techniques for high bandwidth low noise phase-locked loops

Exemplary multipath digital microphones described herein can comprise exemplary embodiments of automatic gain control and multipath digital audio signal digital signal processing chains, which allow low power and die size to be achieved as described herein, while still providing a high DR digital microphone systems. Further non-limiting embodiments can facilitate switching between multipath digital audio signal digital signal processing chains while minimizing audible artifacts associated with either the change in the gain automatic gain control amplifiers switching between multipath digital audio signal digital signal processing chains.

Method for improving die area and power efficiency in high dynamic range digital microphones

In some examples, a circuit includes a clock divider and a calibration circuit coupled to the clock divider. The clock divider includes digital-to-time converter (DTC). The calibration circuit configured to determine a gain error and a parametric integrated nonlinearity (INL) error of the DTC, determine a gain adjustment value and a INL adjustment value to compensate for the gain error and the INL error, and modify operation of the DTC according to the gain adjustment value and the INL adjustment value to correct for the gain error and the INL error.

Calibration of parametric error of digital-to-time converters

In a method for transmit beamforming of a two-dimensional array of ultrasonic transducers, a beamforming pattern to apply to a beamforming space of the two-dimensional array of ultrasonic transducers is defined. The beamforming space includes a plurality of elements, where each element of the beamforming space corresponds to an ultrasonic transducer of the two-dimensional array of ultrasonic transducers, where the beamforming pattern identifies which ultrasonic transducers within the beamforming space are activated during a transmit operation of the two-dimensional array of ultrasonic transducers, such that a generated ultrasonic beam is focused for reflecting from an object in contact with a contact surface of a platen overlying the two-dimensional array of ultrasonic transducers. The beamforming pattern is applied to the two-dimensional array of ultrasonic transducers. A transmit operation is performed by activating the ultrasonic transducers of the beamforming space according to the beamforming pattern.

Transmit beamforming of a two-dimensional array of ultrasonic transducers

A temperature compensated oscillator circuit includes a first oscillator, a second oscillator, a first divider, a second divider, a frequency ratio circuit, and a temperature compensation circuit. The first divider is coupled to the first oscillator, and is configured to divide a frequency of a first oscillator signal generated by the first oscillator. The second divider is coupled to the second oscillator, and is configured to divide a frequency of a second oscillator signal generated by the second oscillator. The frequency ratio circuit is coupled to the first divider and the second divider, and is configured to determine a frequency ratio of an output of the first divider to an output of the second divider. The temperature compensation circuit is coupled to the frequency ratio circuit and the first oscillator, and is configured to generate a compensated frequency based on the frequency ratio and the first oscillator signal.

BAW oscillators with dual BAW temperature sensing

An electronic device includes a plurality of CMOS control elements arranged in a two-dimensional array and a plurality of MEMS devices. Each CMOS control element of the plurality of CMOS control elements includes at least one of a low voltage semiconductor device, a high voltage PMOS semiconductor device, and a high voltage NMOS semiconductor device. Each MEMS device of the plurality of MEMS devices is associated with a CMOS control element of the plurality of CMOS control elements. The plurality of CMOS control elements are arranged in the two-dimensional array such that low voltage semiconductor devices are only adjacent to other low voltage semiconductor devices, high voltage PMOS semiconductor devices are only adjacent to other high voltage PMOS semiconductor devices, and high voltage NMOS semiconductor devices are only adjacent to other high voltage NMOS semiconductor devices.

Two-dimensional array of CMOS control elements

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Nashua, NH, United States of America

Michael Henderson Perrott