Applied Micro Circuits Corporation

Michael Hellmer

Kenneth Yun

Kirk Alvin Miller

George Bendak

Viet Linh Do

Sushil Kumar Singh

Kevin Warren James

Simon Pang

Philip Michael Clovis

David Thomas Dougherty

Jianfeng Shi

Yehuda Azenkot

John David Huber

Matthew D Brown

Hongming An

Mehmet Mustafa Eker

Dimitrios Giannakopoulos

Prayag Bhanubhai Patel

Brian Abernethy

Peter John Holzer

Jim Lew

John Calvin Leung

Ayoob Eusoof Dooply

Eli James Aubrey Fernald

Systems and methods for Phase-Locked Loop (PLL) based frequency synthesizer comprising a dynamic fraction divider in a feedback loop. The dynamic fraction divider employs a dynamic divide ratio that dynamically changes with the jitters and noise spurs contained in an input signal to the PLL, and generates a feedback signal used to adjust the PLL output frequency. The dynamic divide ratio may be determined by comparing the phases of the PLL output signal and the input signal.

Fractional phase-locked loop with dynamic divide ratio adjustment

A system and method are provided for automatic frequency acquisition maintenance in a clock and data recovery (CDR) device. In an automatic frequency acquisition (AFA) mode, the method uses a phase detector (PHD) to acquire the phase of a non-synchronous input communication signal having an initial first frequency. In the event of a loss of lock/loss of signal (LOL/LOS) signal being asserted, a frequency ratio value is retrieved from memory. Using a phase-frequency detector (PFD), the reference signal, and the frequency ratio value, a synthesized signal is generated. In response to using the PFD to generate the synthesized signal and the LOL/LOS signal being deasserted, a rotational frequency detector (RFD) is used to generate a synthesized signal having a frequency equal to the frequency of the input communication signal. With the continued deassertion of the LOL/LOS signal, the PHD is enabled and the phase of the input signal is acquired.

Auto frequency acquisition maintenance in a clock and data recovery device

A system and method are provided for deinterleaving differential inverse multiplexed (DIM) virtual channels in a 40G Ethernet receiver. The method accepts a 10.3125 gigabits per second (Gbps) (10G) Ethernet virtual channel with 64B/86B blocks, including periodic Lane Alignment Marker (LAM) blocks. The 10G virtual channel is deinterleaved into two 5.15625 Gbps (5G) virtual channels by: 1) deinterleaving consecutive blocks from the 10G virtual channel into the 5G virtual channels in an alternating order, and 2) reversing the order of deinterleaving in response to each detected LAM block. Then, the method supplies the 5G virtual channels (i.e. to a MAC module).

Differential inverse multiplexing virtual channels in 40G ethernet applications

A system and method are provided for resynchronizing backplane link management credit counters in a packet communications switch fabric. The method comprises: at an input port card ingress port, accepting information packets including cells and cell headers with destination information; modifying the destination information in the received cell headers; routing information packets between the input port card and output port cards on backplane data links through an intervening crossbar; at the input port card, maintaining a credit counter for each output port card channel; decrementing the counter in response to transmitting cells from the input port card; generating credits in response to transmitting cells from an output port card channel; sending the generated credits to increment the counter, using the modified destination information; and, using the generated credit flow to resynchronize the credit counter.

System and method for synchronizing switch fabric backplane link management credit counters

A system and method are provided for configuring interface bandwidths in a packet communications switch fabric. The method comprises: interfacing data links with a first plurality of traffic managers (TMs); differentiating port card interface ports into a first plurality of subchannels associated with the first plurality of TMs; and, communicating packets information with the TMs at a first plurality of data rates corresponding to the first plurality of subchannels. More specifically, differentiating port card interface ports into a first plurality of subchannels associated with the first plurality of TMs includes: differentiating a second plurality of ingress data links into a third plurality of ingress subchannels associated with a third plurality of ingress traffic managers (iTMs); and, differentiating a fourth plurality of egress data links into a fifth plurality of egress subchannels associated with a fifth plurality of egress TMs (eTMs).

Configurable switch fabric interface bandwidth system and method

A credit-based system and method are provided for managing backplane traffic flow in a packet communications switch fabric. The method comprises: accepting information packets including cells and cell headers with destination information; modifying the destination information in the received cell headers; routing information packets between an input port card and output port cards on backplane data links through an intervening crossbar; at the input port card, maintaining a credit counter for each output port card channel; decrementing the counter in response to transmitting cells from the input port card; generating credits in response to transmitting cells from an output port card channel; and, using modified destination information, sending the generated credits to increment the counter. In some aspects, modifying the destination information in the received packet headers includes: extracting the output port card termination from the card field; and, inserting the input port card source in the card field.

Switch fabric backplane flow management using credit-based flow control

A system and method are provided for cut-through packet routing in a packet communications switch fabric. The method comprises: accepting information packets addressed to a plurality of output port card egress ports at an input port card ingress port; routing information packets between port cards on backplane data links through an intervening crossbar; maintaining a credit counter for each port card egress destination, at the input port card; decrementing the counter in response to transmitting cells in a packet from the input port card; and, incrementing the counter in response to transmitting cells from the packet at the output port card. In some aspects of the method, accepting information includes buffering the packets in an ingress memory subsystem (iMS). Routing information includes the iMS transmitting buffered packets on a selected backplane data link. Decrementing the counter includes the iMS communicating with the iPQ in response to transmitting a cell.

Minimum latency cut-through switch fabric

A system and method are provided for tolerating control link faults in a packet communications switch fabric. The method comprises: accepting information packets including a plurality of cells, at a plurality of port card ports, the plurality of information packets addressing a plurality of port card ports; selectively connecting port card ports to port card backplane data links; in response to backplane control link communications, selectively connecting port card backplane data links and crossbars; sensing a connection fault in a control link; and, in response to sensing the control link fault, reselecting connections between the port card ports and the port card backplane data links. In some aspects, selectively connecting port card backplane data links and crossbars includes: for a particular backplane data link, fixedly connecting each port card to a corresponding interface of an assigned crossbar; and, selectively enabling the connection to each crossbar.

System and method for tolerating control link faults in a packet communications switch fabric

Growing community of inventors

Carlsbad, CA, United States of America

Michael Hellmer