Fairchild Semiconductor Corporation

Michael Harley-Stead

Jun Cai

Jim G Holt

Ronald B Hulfachor

Steven M Leibiger

Daniel J Hahn

Alvin Sugerman

Raymond A Roberts

Eric H Johnson

Jason Woloszyn

An HV PMOS device formed on a substrate having an HV well of a first polarity type formed in an epitaxial layer of a second polarity type includes a pair of field oxide regions on the substrate and at least partially over the HV well. Insulated gates are formed on the substrate between the field oxide regions. Stacked hetero-doping rims are formed in the HV well and in self-alignment with outer edges of the gates. A buffer region of the first polarity type is formed in the HV well between and in self-alignment with inner edges of the gates. A drift region of the second polarity type is formed in the buffer region between and in self-alignment with inner edges of the gates. The drift region includes a region having a gradual dopant concentration change, and includes a drain region of the second polarity type.

Method of fabricating an enhanced resurf HVPMOS device

An asymmetric heterodoped metal oxide (AHMOS) semiconductor device includes a substrate and an insulated gate on the top of the substrate disposed between a source region and a drain region. On one side of the gate, heterodoped tub and source regions are formed. The tub region has dopants of a second polarity. A source region is disposed inside each tub region and has dopants of a first polarity opposite to the second polarity. On the other side of the gate, heterodoped buffer and drift regions are formed. The buffer regions comprise dopants of the second polarity. The drift regions are disposed inside the buffer regions and are doped with dopants of the first polarity. A drain n+ tap region is disposed in the drift region.

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Enhanced RESURF HVPMOS device with stacked hetero-doping RIM and gradual drift region

An asymmetric hetero-doped metal oxide (AHMOS) semiconductor device includes a substrate and an insulated gate on the top of the substrate disposed between a source region and a drain region. On one side of the gate, heterodoped tub and source regions are formed. The tub region has dopants of a second polarity. A source region is disposed inside each tub region and has dopants of a first polarity opposite to the second polarity. On the other side of the gate, heterodoped buffer and drift regions are formed. The buffer regions comprise dopants of the second polarity. The drift regions are disposed inside the buffer regions and are doped with dopants of the first polarity. A drain n+ tap region is disposed in the drift region.

A structure of and a method for making an isolated NMOS transistor using standard BiCMOS processing steps and techniques. No additional masks and processing steps are needed for the isolated NMOS device relative to the standard process flow. A P-type substrate with an overlaying buried N-type layer overlaid with a buried p-type layer below a P-well is shown. An N-type region surrounds and isolates the P-well from other devices on the same wafer. N+ regions are formed in the p-well for the source and drain connections and poly or other such electrical conductors are formed on the gate, drain and source structures to make the NMOS device operational. Parasitic bipolar transistors are managed by the circuit design, current paths and biasing to ensure the parasitic bipolar transistors do not turn on.

Method and structure for BiCMOS isolated NMOS transistor

A system and related process to enable control of photolithographic pattern features on a structure having one or more severe non-flat topologies. The system includes an analysis of the Depth of Focus associated with photolithographic equipment and a photoresist film applied to the structure. From that determination a range of layout dimension of the topologies is identified accordingly and incorporated into the fabrication of such topologies. A conformal layer of material is then applied to the formed structure including the determined topologies to effectively substantially close up the topologies prior to application of the photoresist film. The system is suitable for use with any structure having severe topologies and photolithographic limitations including, for example, in the fabrication of micro-electro mechanical systems.

System to enable photolithography on severe structure topologies

Chemical mechanical polishing (CMP) produces thickness variations over the surface of a chip or die that depends on many factors. The present invention provides for characterization of the thickness variations over the surface area, and accepting these variations in the detailed design of the components that are to be distributed over the entire surface of the die. Any device with parameters that depend on the layer thickness that is subject to CMP will have variations in those parameters depending upon where the device is located on the die. The present invention characterizes the thickness variations and modifies the physical design of other mechanical aspects of the device so as to compensate for the thickness variations. The result is devices that have acceptable parameters regardless of their location on the chip.

Process of compensating for layer thickness by determining device parameters on different surface areas of a substrate

An ESD protection device including a compound transistor structure having a trigger transistor and an ESD protection transistor. The trigger transistor includes a breakdown potential between the standoff voltage of a circuit to be protected and the breakdown potential of the ESD protection transistor. When activated, the trigger transistor operates to turn on the ESD protection transistor that is designed to carry the bulk of the conduction current associated with an ESD event. The trigger transistor is designed with an internal gain mechanism to ensure that it will not be turned off when a modified snapback voltage is reached during the ESD protection transistor operation. The trigger transistor is a minor contributor to the conducting current with the ESD protection transistor after such time as protection circuit operation acts. A process for fabricating a suitable compound transistor structure is disclosed.

Internally triggered electrostatic device clamp with stand-off voltage

An ESD protection device including a transistor structure with resistive regions located within active areas thereof. The transistor structure is formed of one or more MOS transistors, preferably N-type MOS transistors. The drain regions of the transistors are modified to reduce the conductivity of those resistive regions by preventing high carrier concentration implants in one or more sections of the drain regions. This is achieved by modifying an N LDD mask and the steps related thereto, as well as a silicide exclusion mask and the steps related thereto. The modifications result in the omission of N LDD dopant from the area immediately adjacent to the underlying channel. In addition, portions of a spacer oxide remain over the drain region to be formed. Subsequent implant and siliciding steps are effectively blocked by the spacer oxide that remains, leaving a low-density drain (LDD) charge carrier concentration in those regions, except where omitted. The resistivity of those resistive LDD regions is greater than the resistivity of the adjacent portions of the drain region. The result is more uniform turn-on of ESD transistor fingers in a protection device set without the need to add valuable layout space and without increased processing steps.

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Portland, ME, United States of America

Michael Harley-Stead