International Business Machines Corporation

Michael Hans Fisher

Howard Thomas Olnowich

John David Jabusch

Jehoshua Bruck

James William Feeney

Robert Francis Lusch

Arthur Robert Williams

Michael Anthony Maniguet

Joel M Gould

Michael W Dotson

Don Alan Gilliland

John Lee Colbert

Kevin J Przybylski

Eliezer Upfal

Neil A Anderson

Mark L Kyllo

Randall John Fuhrman

Omar A Saiyid

An apparatus that converts and adapts standard processor bus protocol and architecture, such as the MicroChannel bus, to more progressive switch interconnection protocol and architecture. Existing bus-based architecture is extended to perform parallel and clustering functions by enabling the interconnection of thousands of processors. The apparatus is relatively easy to implement and inexpensive to build. The communication media is switch-based and is fully parallel, supporting nodes interconnected by the switching network.

Apparatus for coupling a bus-based architecture to a switch network

A noise attenuating system for suppressing noise on circuit board transmission lines is provided. A first ferrous member is attached to a first side of the circuit board and a second ferrous member attached to a second side of the circuit board. The second ferrous member is substantially opposed from the first ferrous member, such that conductive transmission lines are contained between the first ferrous member and the second ferrous member. Transmission line interference is absorbed and suppressed by the first ferrous member and the second ferrous member. In a preferred embodiment, substantially all traces which enter and exit the circuit board on a connector pass between the first ferrous member and the second ferrous member. Apertures in the circuit board allow the ferrous members to adjoin forming a ferrous core.

Method and system for circuit board common mode noise suppression

The multi-stage interconnection network of the present invention includes the use of switches in the first stage that have parallel path seeking capabilities. With these switches, a directed flash-flood can be instigated from any one node wherein multiple paths through the network to a designated destination node are tried in parallel in an attempt to find a connection path therebetween. The switches in the first and second stages are interconnected such that each switch in the first stage is connected with every possible priority level to the switches of the second stage. The parallel path seeking switches and network are further configured to test for rejection of the flash-flood by monitoring all connections in combination.

Method of simultaneously attempting parallel path connections in a

The present invention addresses the limitations of prior art ALLNODE switches by including dual priority, adaptive, path seeking, and flash-flood functionalities in a single ALLNODE switch. The switch of the present invention further includes a selection device responsive to a selection signal for enabling the selection of the mode of switch operation from any one of the foregoing functionalities. The selection signal is applied to the switch in a number of different ways including: the transmission of a command over the data path interface to the switch; the transmission of a command over special purpose serial or parallel control lines; or via hardwiring. Thus, the selection of functionality for the switch is capable of being made in either a dynamic or static fashion. The present invention further comprises two new high performance networks utilizing the selectable function ALLNODE switch. The networks have a different functionality being performed at each stage, and comprise a 'Multi-Dilated Path Seeking Network' and a 'Nested Path Seeking and Flash-Flood Network.'

Multi-stage interconnection network with selectable function switching

A multi-stage interconnection network includes the use of switches in the first stage that have parallel path seeking capabilities. With these switches, a directed flash-flood can be instigated from any one node wherein multiple paths through the network to a designated destination node are tried in parallel in an attempt to find a connection path therebetween. The switches in the first and second stages are interconnected such that each switch in the first stage is connected with every possible priority level to the switches of the second stage. The parallel path seeking switches and network are further configured to test for rejection of the flash-flood by monitoring all connections in combination.

Flash-flooding multi-stage interconnection network with parallel path

A conversion apparatus that converts and adapts standard processor bus protocol and architecture, such as the MicroChannel (IBM Trademark) bus, to more progressive switch interconnection protocol and architecture. Existing bus-based architecture is extended to perform parallel and clustering functions by enabling the interconnection of thousands of processors. A conversion apparatus controls the transfer of data messages from one nodal element across a switch network to another nodal element by using direct memory access capabilities controlled by intelligent bus masters. This approach does not require interactive support from the processor at either nodal element during the message transmission, and frees up both processors to perform other tasks. The communication media is switch-based and is fully parallel, supporting n transmissions simultaneously, where n is the number of nodes interconnected by the switching network.

Apparatus for adapting message protocols for a switch network and a bus

A modularly expandable switch-based planar apparatus for insertable multiple bus-based processor cards and/or expansion cards and interconnecting the cards via a multi-stage switch network which resides on the planar apparatus. The cards require no modification or change of any kind, since the connection to the planar apparatus is made as if the planar apparatus contained the standard MicroChannel interconnection. The planar apparatus implements bus converter units to convert the standard bus interface provided by the cards to the switch network interface, so that functions provided by the cards can communicate in parallel over the switch network.

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Rochester, MN, United States of America

Michael Hans Fisher