Infineon Technologies Ag

Michael H&uuml;bner

Gunnar H Krause

Peter P&ouml;chm&uuml;ller

Justus Kuhn

Jochen M&uuml;ller

Frank Weber

Jens M&ouml;ckel

Martin Fritz

J&uuml;rgen Weidenh&ouml;fer

Gerrit F&auml;rber

A method for releasable contact-connection of a plurality of integrated semiconductor modules on a wafer, each of which having a plurality of interconnected supply voltage terminals, includes the steps of providing a contacting card for applying external electrical signals to the semiconductor modules with contact elements for releasable electrical connection to terminal pads of the semiconductor modules, aligning the contacting card with the wafer, producing a releasable contact between terminal pads of the plurality of semiconductor modules and the contact elements of the contacting card, checking the contact quality for each of the semiconductor modules by applying a voltage to at least one of the supply voltage terminals of the semiconductor module through the contacting card, measuring the voltage present at a further one of the supply voltage terminals through the contacting card, and using the measurement result to assess whether or not the semiconductor module has correct contact.

Method for releasable contact-connection of a plurality of integrated semiconductor modules on a wafer

A test configuration for testing a plurality of integrated circuits, in particular fast semiconductor memory modules located on a wafer, in parallel. The test configuration includes a carrier board for bringing up electrical signal lines belonging to a test system, contact-making needles for producing electrical connections with contact areas on the circuits to be tested, and a plurality of active modules that are arranged on the carrier board. The active modules are each assigned to one of the circuits to be tested in parallel, and are each case inserted into the signal path between the test system and the associated circuit to be tested. In a preferred embodiment, the active modules are arranged at least partly overlapping, based on a direction at right angles to the plane of the carrier board.

Test configuration and test method for testing a plurality of integrated circuits in parallel

Growing community of inventors

Schönau, Germany

Michael Hübner

Growing community of inventors

Schönau, Germany

Michael H&uuml;bner

Michael Hübner