International Business Machines Corporation

Astrazeneca Ab

Michael H Wood

Stephen Gerard Shuma

Chandramouli Visweswariah

Kerim Kalafala

Debjit Sinha

Eric A Foreman

Chung-Lung K Shum

Jeffrey G Hemmett

Christopher J Berry

Gregory M Schaeffer

Vladimir P Zolotov

David S Wolpert

Michael Richard Ouellette

Brian David Barrick

James Douglas Warnock

Paul Gerard Villarrubia

Natesan Venkateswaran

Aaron Tsai

Alexander Joel Suess

Nathan C Buck

Bradley Nelson

Barry Watson Krumm

James R Mitchell

Eric Jason Fluhr

Jesse Peter Surprise

Sean Michael Carey

Chris Aaron Cavitt

Kenneth Parker Rodbell

Leon Jacob Sigal

Ashokkumar Bhikkappa Shenvi

Chiaming Chai

Adam P Matheny

Jose Luis Neves

Jeffrey Herbert Fischer

Christopher J Gonzalez

Niels Fricke

George E Smith, Iii

David Allan Webber

Hemlata Gupta

Glenn A Biery

Lukas Daellenbach

James Charles Gregerson

Steven Sigmund Wesolowski

Adil Bhanji

Richard G Smith

Dean Brown

Manish Verma

Naiju K Abdul

Phil Edwards

Daniel Mark Boyne

Jennifer E Basile

James Hulsizer

Jeremy J Leitzen

Dan Widzowski

Christian Jacobi

Derek E Williams

Viresh Paruthi

Jente Benedict Kuang

Wolfgang Roesner

Joseph N Kozhaya

William Vincent Huott

Peter Anton Habitz

Gi-Joon Nam

Gustavo Enrique Tellez

Robert Alan Cargnoni

Lakshmi Narasimha Reddy

Hans-Werner Tast

Timothy Gerard McNamara

John P Dubuque

Manjul Bhushan

Vasant B Rao

Basanth Jagannathan

Matthew Mantell Ziegler

Robert Alan Philhower

Alvan Wing Ng

Brian M Dreibelbis

Benedikt Geukes

Ali S El-Zein

Patrick M Williams

Peter Claude Elmendorf

Matthew Thomas Guzowski

Benjamin Neil Trombley

Jinwook Jung

Jason David Morsey

Michael Alexander Bowen

Michael Kazda

Michael R Scheuermann

Ofer Geva

Steven Eugene Washburn

Tsz-mei Ko

Frank Musante

Ravichander Ledalla

Daniel Richard Menard

Guenter Mayer

Geoffrey Wang

Amanda Christine Venton

Klaus-Dieter Schubert

Eric Lee Carter

Eduard Herkel

John Thomas Badar

Aspects of the invention include determining a netlist for an integrated circuit design, wherein the netlist includes a design for placement of a plurality of latches, determining a set of timing paths, wherein each timing path includes a capture latch and at least one launch latch connected to a same local clock buffer controller through a local clock buffer OR circuit, calculating a slack value for each timing path, determining one or more candidate timing paths from the set of timing paths, wherein the one or more candidate timing paths have a slack value below a threshold slack value, calculating a score for each candidate timing path based on a count of a number of launch-capture latch pairs, adjusting an interconnect for a first candidate timing path based on the first candidate timing path having a highest score, and generating an updated netlist based on the adjusting the interconnect.

Netlist design for post silicon local clock controller timing improvement

Method and apparatus for generating an updated power delivery network. Generating the power delivery network includes determining power characteristics for a power delivery network of a circuit design based on logic cells of the circuit design. The power delivery network includes power wires and power staples connecting pairs of the power wires to each other. Further a first one or more of the power staples is remove from the power delivery network based on the power characteristics. Signal wires for the logic cells are routed after removing the first one or more of the power staples. Routing the signal wires includes routing a first signal wire of the signal wires in a routing track corresponding to the first one or more of the power staples.

Generating a power delivery network based on the routing of signal wires within a circuit design

A first plurality of hardware description language (HDL) files describe a hierarchical integrated circuit design utilizing a simplified HDL syntax that omits specification of logical clock connections for at least some entities in the hierarchical integrated circuit design. The hierarchical integrated circuit design as described by the first plurality of HDL files is processed to automatically add logical clock connections for entities in the hierarchical integrated circuit design for which specification of logical clock connections are omitted in the first plurality of HDL files. Based on the processing, a second plurality of HDL files defining the hierarchical integrated circuit design is generated.

Logical clock connection in an integrated circuit design

Embodiments for power generation include defining a power tile within a power distribution network having a grid of power rails, the power tile having logic gates, and applying an initial power grid pattern from a plurality of power grid patterns for the power tile such that initial power grid pattern relates to timing characteristics of the logic gates of the power tile. The power grid patterns each have a different number of connectors connecting one power rail to another power rail in the grid of power rails. A subsequent power grid pattern is selected from the power grid patterns for the power tile such that the subsequent power grid pattern meets a threshold condition for the timing characteristics of the logic gates of the power tile. The timing characteristics for the logic gates are determined based on a voltage drop associated with the subsequent power grid pattern.

Region-based power grid generation through modification of an initial power grid based on timing analysis

A method is provided to increase processor frequency in an integrated circuit (IC). The method includes identifying a gate included in the IC, the gate having a gate threshold voltage and performing a plasma process to form an antenna signal path in signal communication with the gate. The method further comprises adjusting the plasma process or circuit design to increase plasma induced damage (PID) applied to the gate so as to alter the gate threshold voltage.

Processor frequency improvement based on antenna optimization

A clinical event outcome scoring system and method are used to determine a Severity of Illness Clinical Key (SICK) score, which is a probable degree of successful outcome for a patient about to undergo a specific clinical event, such as for example, coronary bypass surgery, hip replacement, bariatric surgery, discharge from a hospital for home recovery, a course of chemotherapy, radiation, or other treatment protocol. The system and method analyzes historical patient data to generate a statistical model for each specific clinical event of interest, which can then be used to determine a SICK score for a patient about to undergo the same clinical event. In some embodiments, the statistical model can be 'fine-tuned' to render subcategories of statistical models tailored for certain patient populations about to undergo the same clinical event. In some embodiments, the statistical model can be augmented to take into account “outliers,” who have extra challenges not taken into account with the primary statistical model.

Clinical event outcome scoring system employing a severity of illness clinical key and method

A system is provided to perform slack apportionment for an integrated circuit. The system includes a time calculation module and a slack apportion module. The time calculation module determines an arrival time corresponding to a target pin in signal communication with a signal path. The slack apportion module determines a total slack associated with the signal path and determines a slack threshold value that is equal to a portion of the total slack. The time calculation module further determines an apportioned arrival time associated with the signal path based on the arrival time and a delay offset value. The slack apportion module further determines a residual slack apportionment value based on a residual slack and the number of macros associated with the signal path. Accordingly, the time calculation module determines a modified apportioned arrival time based on the residual slack apportionment value and the apportioned arrival time.

Even apportionment based on positive timing slack threshold

A statistical single-input switching (SIS) timing value is obtained for a first input of a device. A side input with an arc to a common output of a circuit is selected and a statistical skew for the first input and the selected side input of the circuit is obtained. An expected-value for a statistical scale factor distribution is convolved and computed based on the statistical skew. The statistical single-input switching (SIS) timing value is scaled with a final effective statistical scale factor based on the expected-value; optionally, sensitivities of the statistical timing value to variational parameters are chain-ruled with the sensitivities of the statistical skew to variational parameters; and a statistical timing analysis of a given VLSI design is generated based on the scaled (and optionally, chain-ruled) statistical single-input switching (SIS) timing value to create the improved VLSI circuit design.

Statistical timing analysis considering multiple-input switching

For each of a plurality of source-sink pairs, a corresponding interconnect layer is selected having a reach length which permits propagation of a required signal within a required sink cycle delay. For a first clock cycle, a movable region for a first latch is located as a first plurality of overlapped regions one reach length from a source and the required sink cycle delay number of reach lengths from each one of the sinks; and the first plurality of overlapped regions is represented as nodes on a first cycle level of a topology search graph. Analogous actions are carried out for a second clock cycle of the required sink cycle delay. A latch tree is created based on the topology search graph, wherein a required number of latches is minimized, and at each of the cycle levels, all sinks of source nodes selected at a previous level are covered.

Multi-cycle latch tree synthesis

Efficiency of electronic design automation is increased by accessing a data structure characterizing a hierarchical integrated circuit design including sub-blocks each with a plurality of ports. For each given one of the ports of each of the sub-blocks, obtain a wire specification for a corresponding net connected to the given one of the ports in the design, and based on the wire specification, consult a technology-specific lookup table to determine at least one of a corresponding default driving cell and default electrical model for an external wire coupling one of the default driving cell and an actual driving cell to the given one of the ports. Optimize each of the sub-blocks out-of-context based on the at least one of default driving cells and default electrical models; verify in-context closure for the optimized sub-blocks; and, responsive to the in-context closure, update the data structure to reflect the optimized sub-blocks.

Technology lookup table-based default assertion generation and consumption for timing closure of VLSI designs

A system and method to perform timing analysis in integrated circuit development involves defining an integrated circuit design as nodes representing components of the integrated circuit design that are interconnected by edges representing wires. Sequentially connected nodes define a path. Statistical variables are defined for a canonical delay model of each node and edge of the integrated circuit design and define a first set of conditions. The method includes performing a statistical static timing analysis to obtain an arrival time at each node as a sum of the canonical delay models for nodes and edges that precede the node in the path of the node, obtaining a projected arrival time at a second set of conditions for the node by scaling the arrival time for the node using scale factors that represent the second set of conditions and using a transformation matrix, and providing the integrated circuit design for fabrication.

Superposition of canonical timing value representations in statistical static timing analysis

A design and timing model for at least one circuit path of at least a portion of an IC design is loaded into a computer. At least one canonical clock variable associated with the model is defined; it includes at least one source of variation. The computer is used to perform an SSTA of the at least one circuit path, based on the design and timing model and the at least one canonical clock variable, to obtain slack canonical data. A clock period is projected, based on the slack canonical data, such that a cycle time canonical is projected to a different space than a logic canonical. Results of the SSTA and the projected clock period are output to determine performance compliance. Efficient operation of the computer is enhanced by analyzing a slack vector in a single timing run, loaded once, and multithreading timing propagation.

Independently projecting a canonical clock

A method, system, and compute program product use a generalized macro or a generalized macro timing abstract for timing analysis in a specific timing context. The method includes setting up a timer, and determining a divide ratio of each external clock divider of one or more external clock dividers associated with the generalized macro or the generalized macro timing abstract programmatically as a function of another value. The method also includes performing the timing analysis using the divide ratios of the one or more external clock dividers. Obtaining a physical implementation of an integrated circuit is based on the timing analysis.

Programmable clock division methodology with in-context frequency checking

Coupled noise from at least one out-of-context aggressor net of an integrated circuit design is computed for an out-of-context victim net. The nets are out-of-context with respect to a hierarchical noise analysis of the integrated circuit design. At least one of the nets is a continuation of a path which extends to at least one in-context portion of the integrated circuit design. An aggressor signal timing window is derived for the at least one out-of-context aggressor net; a victim signal timing window is derived for the out-of-context victim net; and a timing window and noise analysis is completed with the aggressor signal timing window and the victim signal timing window. The aggressor window is derived as a function of required arrival time of the at least one out-of-context aggressor net and/or the victim window is derived as a function of required arrival time of the out-of-context victim net.

Using required arrival time constraints for coupled noise analysis and noise aware timing analysis of out-of-context (OOC) hierarchical entities

Growing community of inventors

Hopewell Junction, NY, United States of America

Michael H Wood