International Business Machines Corporation

Kabushiki Kaisha Toshiba

Michael H Sitko

John Maxwell Cohn

Ronald Dennis Rose

Atsushi Kameyama

Mark Eliot Masters

Judith H McCullen

Karen Ann Bard

Sarah C Braasch

Richard Dauphin

Matt Boucher

Sunil Konanki

The invention provides a method, system, and program product for diagnosing an integrated circuit. In particular, the invention captures one or more images for each relevant circuit layer of the integrated circuit. Based on the image(s), a component netlist is generated. Further, a logic netlist is generated by applying hierarchical composition rules to the component netlist. The component netlist and/or logic netlist can be compared to a reference netlist to diagnose the integrated circuit. The invention can further generate a schematic based on the component netlist or logic netlist in which components are arranged according to port, power, and/or component pin connection information determined from the netlist. Further, the schematic can be displayed in a manner that wiring connections are selectively displayed to assist a user in intelligently arranging the circuit components.

Integrated circuit diagnosing method, system, and program product

Systems and methods for the noise analysis of circuits are presented. These systems and methods may allow a circuit or circuit design to be analyzed for possible noise failures in a block of logic caused by sources. outside the block. More particularly, these systems and methods may generate an abstract file for one or more blocks of a circuit. These abstract files may include noise tolerances for input pins and bi-directional pins of a block, along with noise tolerances for those output pins of the block which also feed to an input of one or more gates internal to the block. Using these noise abstracts a unit of the circuit may be analyzed, or the circuit itself may be analyzed for possible noise induced failures.

System and method for circuit noise analysis

A method, system and program product for designing an integrated circuit (IC) for signal integrity. The invention conducts a signal integrity analysis on an IC design; identifies any field effect transistor (FET) that causes a signal integrity failure in the case that the IC design fails the signal integrity analysis; and modifies an edge of a failing FET that is closer than a threshold distance to a well edge. The invention eliminates the manual, iterative procedure for determining the device causing a signal integrity failure due to well proximity effects.

Integrated circuit design for signal integrity, avoiding well proximity effects

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Jericho, VT, United States of America

Michael H Sitko