Other

Infineon Technologies Ag

Universitaet Potsdam

Michael Gössel

Egor Sogomonyan

Thomas Kern

Jan Otterstedt

Thomas Rabenalt

Daniel Marienfeld

In various embodiments, a method of using a memory device is provided. The method may include storing data units, check units of a first code and check units of a second code in memory cells of the memory device, wherein the data units and the check units of the first code form code words of the first code, and wherein the data units and the check units of the second code form code words of the second code, applying the second code for error correction in at least a portion of the data units and/or in at least a portion of the check units of the first code, after the correcting the errors, retaining at least a retaining portion of the data units and of the check units of the first code and deleting at least a deleting portion of the check units of the second code, thereby freeing the memory cells that are occupied by the deleting portion of the check units of the second code, and during a subsequent using of the memory device, storing data in at least a reuse portion of the freed-up memory cells.

Method of using a memory device, memory device and memory device assembly

The invention relates to a circuit arrangement, comprising: a functional circuit with m (m=1, 2, . . . ) data inputs and n (n=1, 2, . . . ) data outputs for processing at least one m-dimensional binary data input (x, . . . , xm) to form an n-dimensional data output (y, . . . , yn), wherein the functional circuit comprises at least one combinatorial circuit part, at least two registers with a word length k (k=1, 2, . . . ; k&#x2266;n) which are coupled to at least some of the n data outputs of the functional circuit in order to store output values (y=y, . . . , yk; y'=y&#x2032;, . . . , y&#x2032;k) which are duplicated with respect to one another or are duplicated with bit-by-bit inversion with respect to one another, said output values being derived from the n-dimensional data output (y, . . . , yn) of the functional circuit, at least one corrector with an input word length 2k and an output word length k, which is coupled to data outputs of the at least two registers and supplies a k-dimensional corrected data output (y[k](korr)=y(korr), . . . , yk(korr)), and an error detection circuit for detecting errors during operation of at least one of the aforementioned circuit elements: the functional circuit, the at least two registers and the corrector.

Circuit arrangement

The invention relates to a circuit for comparing two n-digit binary data words x[1](t), . . . , x[n](t) and x'[1](t), . . . , x&#x2032;[n](t), which in the error-free case are either identical or inverted bit-by-bit with respect to each other, with a series connection of a combinatorial circuit for implementing a first combinatorial function, a controllable register and a combinatorial circuit for implementing another combinatorial function.

Circuit for comparing two N-digit binary data words

Growing community of inventors

Mahlow, Germany

Michael Gössel