Advanced Micro Devices Corporation

Globalfoundries Inc.

Michael Grell

Ralf Findeisen

Frank Schuecke

Matthias Lenk

Uwe Eckhardt

Richard Powell

Michael Fiedler

Axel Wachtler

Marc Edwin Jones

Tim Edward Perley

A secure boot processing may be accomplished on the basis of a non-volatile memory that is an integral part of the CPU and which may not be modified once a pre-boot information may be programmed into the non-volatile memory. During a reset event or a power-on event, execution may be started from the internal non-volatile memory, which may also include public decryption keys for verifying a signature of a portion of a boot routine. The verification of the respective portion of the boot routine may be accomplished by using internal random access memories, thereby avoiding external access during verification of the boot routine. Hence, a high degree of tamper resistance may be obtained, for instance, with respect to BIOS modification by exchanging BIOS chips.

Computer system comprising a secure boot mechanism

A CPU, a computer system and a secure boot mechanism are provided in which a symmetric encryption key may be incorporated into a non-volatile memory area of the CPU core, thereby substantially avoiding any tampering of the encryption key by external sources. Moreover, pre-boot information may be internally stored in the CPU and may be retrieved upon a reset or power-on event in order to verify a signed boot information on the basis of the internal symmetric encryption key. Furthermore, the BIOS information may be efficiently updated by generating a signature using the internal encryption key.

Computer system comprising a secure boot mechanism on the basis of symmetric key encryption

A software development technique is provided using target system virtualization software simulating behaviour of a target system. A target device driver running on a host system issues memory access commands to the target system virtualization software rather than to a memory interface unit of the host system. The memory interface unit may be an SRAM (Static Random Access Memory) interface. The target system may be an EGPRS (Enhanced General Packet Radio Service) modem.

Memory access to virtual target device

The present invention relates methods for patching WWAN (Wireless Wide Area Network) communication devices and corresponding WWAN communication devices, integrated circuit chips and computer-readable media. The WWAN communication device includes a first processor, a second processor and a memory. The first processor is arranged to process patches updating software running on the WWAN communication device. The second processor is arranged to provide a first set of the patches to the first processor. The memory stores a second set of the patches to be processed by the first processor. The second processor is further arranged to send a patch end signal to the first processor, the patch end signal causing the first processor to stop processing of patches provided by the second processor. The first processor is further arranged to process the patches stored in the memory independently of the patch end signal.

Secure patch installation for WWAN systems

A WLAN (Wireless Local Area Network) transmitter or another data communications apparatus is provided that includes a transmission section that is configured to generate signals to be transmitted, and a control section that is connected to the transmission section to control the transmission section dependent on at least two transmission parameters. The control section comprises a state transition controller that is configured to step through a plurality of predefined control states. The control section is configured to apply different transmission parameter modification mechanisms in different control states. The state transition controller is configured to determine the respective next control states based on transmission success and failure statistics.

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Dresden, Germany

Michael Grell