Atmel Germany Gmbh

Atmel Corporation

Telefunken Semiconductors Gmbh & Co. Kg

Other

Robert Boschgmbh

Eberhard-karls-universität Tübingen Universitätsklinikum

Eberhard-karls-universitat Tubingen Universitatsklinkum

Michael Graf

Volker Dudek

Franz Dietz

Stefan Schwantes

Manfred Klaussner

Gayle W Miller

Christoph Bromberger

Martin Stelzle

Wilfried Nisch

Alfred Stett

Eberhart Zrenner

Heinz Gerhard Graf

Joern Herrfurth

Irwin Rathbun

Alan L Renninger

Stefan Weiss

Markus Schubert

Peter Grombach

James Shen

Thomas Hoffmann

Timo Seitzinger

Hugo Hämmerle

Henning Lohmeyer

Anke Hierzenberger

Markus B Schubert

Julia Rauh

Gayle W Miller, Jr

Helmut Sachs

Hugo Hammerle

Elke G&uuml;nther

Harald N Wanka

Tobias Florian

A protective circuit against electrostatic discharges for connection pins of an application-specific integrated circuit. The protective circuit includes a first connection pin and a second connection pin, and the first connection pin and the second connection pin being connected to one another in a Y configuration. Moreover, an application-specific integrated circuit including a protective circuit of this type is provided.

Protective circuit against electrostatic discharges

A device for detecting a number of electrostatic discharges including a discharge protection unit, in which a detection unit is electrically connected in parallel to the discharge protection unit and the detection unit generates an output signal, which represents the number of electrostatic discharges. A related method is also described.

Device and method for detecting a number of electrostatic discharges

By aligning the primary flat of a wafer with a () plane rather than a () plane, devices can be formed with primary currents flowing along the () plane. In this case, the device will intersect the () plane at approximately 54.7 degrees. This intersect angle significantly reduces stress propagation/relief along the () direction and consequently reduces defects as well as leakage and parasitic currents. The leakage current reduction is a direct consequence of the change in the dislocation length required to short the source-drain junction. By using this technique the leakage current is reduced by up to two orders of magnitude for an N-channel CMOS device.

Low leakage FINFETs

A method and system for fabricating a stacked capacitor and a DMOS transistor are disclosed. In one aspect, the method and system include providing a bottom plate, an insulator, and an additional layer including first and second plates. The insulator covers at least a portion of the bottom plate and resides between the first and second top plates and the bottom plate. The first and second top plates are electrically coupled through the bottom plate. In another aspect, the method and system include forming a gate oxide. The method and system also include providing SV well(s) after the gate oxide is provided. A portion of the SV well(s) resides under a field oxide region of the device. Each SV well includes first, second, and third implants having a sufficient energy to provide the portion of the SV well at a desired depth under the field oxide region without significant additional thermal processing. A gate, source, and drain are also provided.

Method and system for incorporating high voltage devices in an EEPROM

A lateral DMOS-transistor is provided that includes a MOS-diode made of a semi-conductor material of a first type of conductivity, a source-area of a second type of conductivity and a drain-area of a second type of conductivity which is separated from the MOS-diode by a drift region made of a semi-conductor material of a second type of conductivity which is at least partially covered by a dielectric gate layer which also covers the semi-conductor material of the MOS-diode. The dielectric gate-layer comprises a first region of a first thickness and a second region of a second thickness. The first region covers the semi-conductor material of the MOS-diode and the second region is arranged on the drift region. A transition takes place from the first thickness to the second thickness such that an edge area of the drift region which is oriented towards the MOS-diode is arranged below the second area of the gate layer. The invention also relates to a method for the production of these types of DMOS-transistors.

Lateral DMOS transistor and method for the production thereof

A method for manufacturing a metal-semiconductor contact in semiconductor Components is disclosed. There is a relatively high risk of contamination in the course of metal depositions in prior-art methods. In the disclosed method, the actual metal -semiconductor or Schottky contact is produced only after the application of a protective layer system, as a result of which it is possible to use any metals, particularly platinum, without the risk of contamination.

Method for manufacturing a metal-semiconductor contact in semiconductor components

A method for producing deep trench structures in an STI structure of a semiconductor substrate is provided, with the following successive process steps: subsequent to a full-area filling of STI recesses introduced into a semiconductor substrate with a first filler material, a first surface of a semiconductor structure is subjected to a CMP process to level the applied filler material and produce the STI structure; the leveled STI structure thus produced is structured; using the structured, leveled STI structure as a hard mask, at least one deep trench is etched in the area of this STI structure to create the deep trench structures.

Method for producing deep trench structures

An electrostatic discharge (ESD) protection structure is disclosed. The ESD protection structure includes an active device. The active device includes a plurality of drains. Each of the drains has a contact row and at least one body contact row. The at least one body contact row is located on the active device in a manner to reduce the amount of voltage required for triggering the ESD protection structure.

Electrostatic discharge (ESD) protection structure and a circuit using the same

A lateral DMOS transistor is disclosed that includes a first region of a first conductivity type, which is surrounded on the sides by a second region of a second conductivity type, whereby a boundary line between both regions has opposite straight sections and curved sections linking the straight sections, and with a first dielectric structure, which serves as a field region and is embedded in the first region and surrounds a subregion of the first region. Whereby the first distance between the first dielectric structure and the boundary line is greater along the straight sections than along the curved sections.

DMOS transistor with optimized periphery structure

High-voltage field-effect transistor is provided that includes a drain terminal, a source terminal, a body terminal, and a gate terminal. A gate oxide and a gate electrode, adjacent to the gate oxide, is connected to the gate terminal. A drain semiconductor region of a first conductivity type is connected to the drain terminal. A source semiconductor region of a first conductivity type is connected to the source terminal. A body terminal semiconductor region of a second conductivity type is connected to the body terminal. A body semiconductor region of the second conductivity type, is partially adjacent to the gate oxide to form a channel and is adjacent to the body terminal semiconductor region. A drift semiconductor region of the first conductivity type is adjacent to the drain semiconductor region and the body semiconductor region, wherein in the drift semiconductor region, a potential barrier is formed in a region distanced from the body semiconductor region.

High-voltage field-effect transistor

A method of fabricating an electronic device and a resulting electronic device. The method includes forming a pad oxide layer on a substrate, forming a silicon nitride layer over the pad oxide layer, and forming a top oxide layer over the silicon nitride layer. A first dopant region is then formed in a first portion of the substrate. A first portion of the top oxide layer is removed; a remaining portion of the top oxide layer is used to align a second dopant mask and a second dopant region is formed. An annealing step drives-in the dopants but oxygen diffusion to the substrate is limited by the silicon nitride layer; the silicon nitride layer thereby assures that the uppermost surface of the silicon is substantially planar in an area proximate to the dopant regions after the annealing step.

DMOS device with sealed channel processing

A method of fabricating an electronic device and the resulting electronic device. The method includes forming a gate oxide on an uppermost side of a silicon-on-insulator substrate; forming a first polysilicon layer over the gate oxide; and forming a first silicon dioxide layer over the first polysilicon layer. A first silicon nitride layer is then formed over the first silicon dioxide layer followed by a second silicon dioxide layer. Shallow trenches are etched through all preceding dielectric layers and into the SOI substrate. The etched trenches are filled with another dielectric layer (e.g., silicon dioxide) and planarized. Each of the preceding dielectric layers are removed, leaving an uppermost sidewall area of the dielectric layer exposed for contact with a later-applied polysilicon gate area. Formation of the sidewall area assures a full-field oxide thickness thereby producing a device with a reduced-electric field and a reduced capacitance between gate and drift regions.

Methods of forming reduced electric field DMOS using self-aligned trench isolation

A first mark, in a double-well integrated circuit technology, is formed by a first etching of a first mask layer on top of an ONO stack. After a first well is doped, a second etching occurs at the first etching sites in the uppermost layer of oxide of the ONO stack forming a first alignment artifact. A second mask layer is applied after removing the first mask layer. A second well doping occurs at second mask layer etching sites to maintain clearance between the two wells within active areas and provide an overlap of the two wells in a frame area. At the first alignment artifact in the overlap of the two wells, further etchings remove remaining layers of the ONO stack and remove silicon from the upper most layer of the semiconductor forming a second registration mark, which may be covered by a protective layer.

Registration mark within an overlap of dopant regions

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Leutenbach, Germany

Michael Graf