Xcerra Corporation

Ltx Corporation

Michael Gordon Davis

William A Fritzsche

Timothy Alton

Russell Elliott Poffenberger

Jeffery D Currin

Phillip D Burlison

Mark E Deome

Tommie Edward Berry

Donald Vick Organ

Christopher Joel Hannaford

David W Curry

Eric H Rosenfeld

David Menis

Kenneth J Lanier

Roger W Blethen

H Neil Kelly

Jeffrey H Perkins

Edward J Terrenzi

A scalable test platform includes a PCIe-based event fabric. One or more CPU subsystems are coupled to the PCIe-based event fabric and configured to execute an automated test process. One or more instrument subsystems are coupled to the PCIe-based event fabric and configured to interface one or more devices under test.

Scalable test platform in a PCI express environment with direct memory access

A scalable test platform includes a PCIe-based event fabric. One or more instrument subsystems are coupled to the PCIe-based event fabric and configured to interface one or more devices under test and generate captured test data. One or more digital signal processing subsystems are coupled to the PCIe-based event fabric and configured to process the captured test data.

A method, computer program product, and computing system for, upon the occurrence of a computer-related event, comparing code utilized by one or more subsystems included within a scalable test platform to code available from a remote location. If the code available from the remote location is newer than the code utilized by one or more subsystems, the code available from the remote location is obtained, thus defining newer code. The code utilized by one or more subsystems is updated with the newer code.

Scalable test platform

An electronic tester with digital, and analog, and memory test circuitry on a single platform. A test head is coupled to a device under test. The device under test can be a system-on-a-chip integrated circuit, a mixed signal integrated circuit, a digital integrated circuit, or an analog integrated circuit. Digital test circuitry applies digital test signals to the device under test coupled to the test head and receives digital outputs from the device under test in response to the digital test signals. Analog test circuitry applies analog test signals to the device under test coupled to the test head and receives analog outputs from the device under test in response to the analog test signals. Memory test circuitry applies memory test patterns to the device under test coupled to the test head and receives memory outputs from the device under test in response to the memory test patterns. A tester computer supervises the application of digital, analog, and memory test signals from the digital, analog, and memory test circuitry to the device under test such that signals applied to the device under test can be solely digital test signals, solely analog test signals, solely memory test signals, or mixed digital, analog, and memory test signals. The test head, the digital test circuitry, the analog test circuitry, the memory test circuitry, and the computer are operable as a single platform.

Single platform electronic tester

Growing community of inventors

San Jose, CA, United States of America

Michael Gordon Davis