Infineon Technologies Ag

Universität Potsdam

Michael Goessel

Thomas Kern

Thomas Rabenalt

Ulrich Backhausen

Christian Badack

Klaus Oberlaender

Karl Hofmann

Georg Georgakos

Andreas Leininger

Berndt Gammel

Michael Dieter Richter

Steffen Sonnekalb

Franz Klug

Matthias Beck

Egor Sogomonyan

Peter Muhmenthaler

Sven Hosp

Frank Poehl

Jan Rzeha

Alexander Klockmann

Albrecht Mayer

Jan Otterstedt

Rainer Goettfert

Glenn Ashley Farrall

Heinz Mattes

Simon Brewerton

Neil Stuart Hastie

Antonio Vilela

Jens Rosenbusch

Sebastian Sattler

David Addison

Jorge Guajardo Merchan

Michael Augustin

Anton Huber

Rainer Faller

Boyko Traykov

Holger Bock

Jayachandran Bhaskaran

Stéphane Lacouture

Roland Brachmann

Rolf Kraemer

Guenther Niess

Jessica Trebst

Klaus Oberländer

Georg Duchrau

Solutions are proposed related to error detection wherein (i) each byte of a second byte sequence is determined as a function of at least one byte of a first byte sequence, (ii) a byte of the second byte sequence is impermissible if it is not equal to an assigned byte of the first byte sequence and if no error of a predefined error set corrupts this byte to the assigned byte of the first byte sequence, and (iii) at least one error is detected if the second byte sequence is impermissible, the second byte sequence being impermissible if at least one byte of the second byte sequence is impermissible.

Error detection

An approach to correcting errors in a string of symbols is proposed, in which the string of symbols is transformed by a transformation τ into a first group of symbols and into a second group of symbols, and in which the group of symbols that has fewer erroneous symbols than the other group is corrected using a first error code.

Error correction with error code for a string of symbols

What is proposed is a solution for processing errors in a sequence of bits, wherein the sequence of bits, in the error-free case, forms a codeword of an error code, wherein the error code is based on an H-matrix or is able to be determined thereby, wherein an error syndrome is determined for the sequence of bits, wherein a link is determined between components of the error syndrome and parts of the H-matrix, and wherein two adjacent bits in the sequence of bits are corrected if the link adopts a predefined value.

Error processing and correction of adjacent 2-bit errors

An approach for correcting at least one byte error in a binary sequence is proposed, the binary sequence comprising a plurality of bytes and being a code word of an error code in the error-free case. The approach comprises the steps of: (i) determining at least one byte error position signal which specifies whether or not a byte of the binary sequence is erroneous, (ii) determining at least one byte error correction value, based on which an erroneous byte position identified by means of the byte error position signal is correctable, the at least one byte error correction value being determined by virtue of a first value and a second value being determined for each of at least two byte positions based on a coefficient of the locator polynomial, and (iii) correcting the at least one byte error based on the at least one byte error correction value.

Byte error correction

A solution is proposed for error processing, wherein n byte error positions of n byte errors are predefined (where n is a positive integer), wherein this involves determining whether there is a further byte error position on the basis of the n byte error positions and on the basis of n+1 error syndrome components of a first error code.

Error processing for non-volatile memories

A method for storing data bits in memory cells, in which the data bits have at least one byte-filling bit, where at least one predefined functionality for a subset of the data bits is coded in the at least one byte-filling bit, and in which the data bits are stored in the memory cells. A method for reading data bits from memory cells, in which the data bits have at least one byte-filling bit, where at least one predefined functionality for a subset of the data bits is coded in the at least one byte-filling bit, and in which the data bits are read from the memory cells based on the coded predefined functionality. Corresponding apparatuses and memories are also disclosed.

Method for memory storage and access

A method for determining a resultant data word when accessing memory cells includes reading a set of memory cells, and determining first and second data words therefrom. Each memory cell is assigned a component of the first and second data words. The first and second data words for the respective memory cell assume a first value if a first comparison with a first reference value and a second comparison with a second reference value show that the two reference values are greater and assume a second value if the first comparison with the first reference value and the second comparison with the second reference value show that the two reference values are smaller. The first and second data words assume at least one third value if neither condition is satisfied. The resultant data word is determined based on the first or second data words. A corresponding device is also proposed.

Determination of a resultant data word when accessing a memory

Processing of a bit sequence is proposed, wherein (i) a first partial error syndrome sof an error syndrome and a second partial error syndrome sof the error syndrome are determined for the bit sequence, (ii) a first comparison value is determined on the basis of a bit position and the first partial error syndrome, (iii) a second comparison value is determined on the basis of the bit position and the second partial error syndrome, and (iv) the bit position is corrected should a comparison of the first comparison value with the second comparison value assume a specified value and otherwise the bit position is not corrected.

Correction of bit errors

A method for detecting an address error when reading a bitstream from a memory is proposed, wherein a check is carried out as to whether the bitstream in conjunction with the present read address is a code word of an error code and wherein, should the bitstream in conjunction with the present read address not be a code word of the error code, an address error is subsequently detected provided the error code does not correct an error correctable thereby. Accordingly, an apparatus, a system and a computer program product are specified.

Detecting address errors

A method and associated apparatus is disclosed for processing data by means of an error code, wherein the error code has an H-matrix with n columns and m rows, wherein the columns of the H-matrix are different, wherein component-by-component XOR sums of adjacent columns of the H-matrix are different from one another and from all columns of the H-matrix and wherein component-by-component XOR sums of nonadjacent columns of the H-matrix are different from all columns of the H-matrix and from all component-by-component XOR sums of adjacent columns of the H-matrix.

Processing of data

Method for determining a resultant data word when accessing memory cells of a memory, comprising the steps: (a) reading a set of memory cells, (b) wherein a first data word and a second data word are determined from the read set of memory cells, wherein each memory cell is assigned a component of the first data word and the corresponding component of the second data word, (c) wherein the first data word and the second data word for the respective memory cell assume a first value if a first comparison with a first reference value and a second comparison with a second reference value show that the two reference values are greater and assume a second value if the first comparison with the first reference value and the second comparison with the second reference value show that the two reference values are smaller, (d) wherein the first data word and the second data word for the respective memory cell assume at least one third value if the conditions according to feature (c) are not satisfied, and (e) determining the resultant data word on the basis of the first data word or on the basis of the second data word. A corresponding device is also proposed.

A method for detecting a code word is proposed, wherein the code word is a code word of one of at least two codes, wherein n states are read from memory cells of a memory, respectively. The n states are determined in a time domain for each of the at least two codes, wherein additionally n states are read from further memory cells and at least one reference value is determined therefrom and wherein the at least one reference value is taken as a basis for determining which of the at least two codes is the correct code. A corresponding device is furthermore specified.

Detection of codewords

In an embodiment, a storage device includes a multiplicity of data value memory cells and a multiplicity of check value memory cells, where at least one of the multiplicity of data value memory cells is assigned to two of the check value memory cells, and where at least one of the multiplicity of check value memory cells is assigned to two of the data value memory cells, and a correction circuit which is configured to output a corrected data value when reading out a selected data value memory cell of the at least one of the multiplicity of data value memory cells, based on a content of the selected data value memory cell and based on contents of the two check value memory cells assigned to the selected data value memory cell.

Devices and methods for data storage

What is specified is a method for transforming a first binary signal read from a memory, wherein the first binary signal is transformed into a second binary signal provided that the first binary signal is a code word or a predefined code word of a k-out-of-n code, wherein the first binary signal is transformed into a predefined signal provided that the first binary signal is not a code word or is not a predefined code word of the k-out-of-n code, wherein the predefined signal is different than the second binary signal. A corresponding device is furthermore specified.

Transformation of binary signals read from a memory

Systems, methods, and circuitries are disclosed for protecting data throughout read and write operations. In one example a method includes receiving a plurality of data bits; dividing the plurality of data bits into at least two data blocks; generating respective sets of block check bits for each respective data block using a respective first error code; combining the sets of block check bits to generate a set of signature bits for the plurality of data bits; generating a set of cumulative check bits for the plurality of data bits and the set of signature bits using a second error code; and storing, in a memory location, the plurality of data bits, the set of signature bits, and the set of cumulative check bits.

Continuous error coding

Growing community of inventors

Mahlow, Germany

Michael Goessel