Altera Corporation

Tabula, Inc.

Michael Glenn Wrighton

Christopher D Ebeling

Andrew Edward Caldwell

Kent R Townley

Michael Alan Baxter

David Bruce Parlour

An integrated circuit (IC) that includes multiple clock domains is provided. Each clock domain operates at a user specified data rate, and the data rates of at least two of the clock domains are related by a common base clock. The specified data rate of each clock domain is controlled by a modulating signal. Each clock domain includes reconfigurable circuits that operate on the common base clock, and the modulating signal controls the data rate of the clock domain by modulating reconfiguration of the reconfigurable circuits. The reconfigurable circuits reconfigure when the modulating signal enables the reconfiguration.

Implementation of related clocks

A structure for a parallel cyclic redundancy check (CRC) structure in which the number of cycles in the loopback can be arbitrarily extended is provided. The parallel CRC structure includes a reweighting module in the feedback loop that is pipelined into multiple stages. The parallel CRC structure also includes multiple feed forward reweighting modules that correspond to the multiple pipeline stages in the feedback loop. The reweighting module in the feedback loop accumulates and reweights the contribution of all symbols in the message, while the N reweighting modules in the N parallel feed-forward paths provide the contributions of the symbols that are 'in-flight' within the feedback loop to the final CRC checksum.

CRC circuits with extended cycles

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Boulder, CO, United States of America

Michael Glenn Wrighton