International Business Machines Corporation

Michael Gerard Nealon

Bradley David McCredie

Roger Ned Bailey

Joseph L Temple, Iii

John J Ellison

Dennis Felix Clocher

Hugh Rodney Stigdon

Joseph John Lisowski

A multi-chip apparatus is disclosed. In one form, the apparatus includes a carrier having a number of integrated circuit chips electrically coupled in a communications ring. The communications ring has carrier portions on the carrier and chip portions traversing the respective chips, permitting the communications ring carrier portions to be substantially straight, whereas at least one of the chip portions has a turn, enabling closure of the ring. In another aspect, the chips include respective regeneration circuitry interposed in the respective chip portions of the communications ring, for regenerating communications signals traversing the respective chips on the respective chip portions of the ring.

Multi-chip module having chips coupled in a ring

An integrated circuit chip has a first i/o set associated with a first edge of the chip and a second i/o set associated with a second edge of the chip. The first i/o set has a physical symmetry with respect to the second i/o set, to facilitate a number of the chips being interconnected in a ring to one another on a multi-chip module, with the chips symetrically disposed thereon. The chip has a bus interconnecting the first and second i/o sets for transmitting signals across the chip. The bus has regeneration circuitry for regenerating said signals traversing the chip.

Integrated circuit chip with features that facilitate a multi-chip module having a number of the chips

A pre-production, prototype multi-chip module adapted for preliminary performance timing and functional tests includes a plurality of chips attached to a substrate. Multiple nets are embedded within the substrate connecting the chips. A layer over the substrate encapsulates the chips. Production input/output pins on the substrate are connected to the chips. An area on the upper surface of the module is not covered by the encapsulating layer, which contains upper pads adapted for connection of a second module containing spare circuits to the substrate, wherein the upper pads are connected to the at least one net. Some of the upper pads have connections to each other near the surface of the encapsulating layer, wherein the connections are adapted to be severed for connecting a second module containing spare circuits to one or more of the chips.

Prototyping multichip module

Growing community of inventors

Cedar Park, TX, United States of America

Michael Gerard Nealon