Dalsa Corporation

Teledyne Rad-Icon Imaging Corp.

Michael George Farrier

Stacy R Kamasz

Charles Russell Smith

Eric Charles Fox

Michael Miethig

Suhail Agwani

John Bernard Roumbanis

A charge coupled device includes first and second pluralities of column registers and first and second register segments. The first plurality of column registers are splayed with respect to and on one side of a column direction line, and the second plurality of column registers are splayed with respect to and on another side of the column direction line. The first register segment is coupled to the first plurality of column registers, and the second register segment is coupled to the second plurality of column registers. The second register segment is spaced apart from the first register segment so as to define a layout area between the first and second register segments where at least one of an isolation register element and an output node is disposed. Each column register of the first plurality of column registers includes a plurality of column element wells. The column element wells of all of the first plurality of column registers constitute a plurality of well rows where each of the plurality of well rows is splayed with respect to a row direction line.

Architecture for a tapped CCD array

A fast frame interline transfer charge coupled device imaging sensor includes an imaging section and an storage section. The imaging section includes a plurality of interline transfer registers, each interline transfer register containing a plurality of interline register elements. The imaging section further includes an interline clocking structure, the interline clocking structure including polycrystalline silicon buss lines used as gate electrodes, the polycrystalline silicon buss lines being connected to a metal strapping network, the interline clocking structure causing charge to be transferred between interline register elements of each interline transfer register based on interline clocking signals. The storage section is coupled to the imaging section. The storage section includes a plurality of storage registers, each storage register containing a plurality of storage register elements. The storage section further includes a storage discharge structure and a storage clocking structure. Each storage register element of the storage registers is selectively coupleable through the storage discharge structure to a storage drain. The storage clocking structure has first and second clocking structure parts, the first clocking structure part corresponding to first storage register elements coupled to respective interline registers. The first clocking structure part is coupled to the interline clocking structure so as to cause charge to be transferred from the respective interline registers to the first storage register elements based on the interline clocking signals. The second clocking structure part causes charge to be transferred between storage register elements of each storage register based on frame clocking signals.

Image smear and dark signal reduction device and method

In a charge coupled device having a plurality of output structures, the plurality of output structures including first and second output structures, a channel structure is defined in a channel region beneath a gate electrode and coupled to each of the plurality of output structures. The channel structure includes a plurality of area structures, each area structure being characterized by a uniform potential which is different from the potential characterizing each of the other area structures. The plurality of area structures are arranged within the channel region to define a first increasing stepped potential gradient from any point within the channel region to the first output structure and define a second increasing stepped potential gradient from any point within the channel region to the second output structure. A length of each area structure traversing the area structure in a first gradient direction is less than or equal to a first critical length, the first critical length being defined by a first desired transfer time for transferring charge to the first output structure. A length of each area structure traversing the area structure in a second gradient direction is less than or equal to a second critical length, the second critical length being defined by a second desired transfer time for transferring charge to the second output structure.

Efficient charge transfer structure in large pitch charge coupled device

A CCD shift register includes a second gate electrode disposed adjacent to and longitudinally spaced from a first gate electrode, and a buried layer having a first dopant impurity concentration. The first gate electrode is disposed over the buried layer to define a first buried layer area. The second gate electrode is disposed over the buried layer to define a second buried layer area greater than the first buried layer area. In the buried layer, a trench region is formed to have a second dopant impurity concentration greater than the first dopant impurity concentration. The first gate electrode is disposed over the trench region to define a first trench area. The second gate electrode being disposed over the trench region to define a second trench area less than the first trench area. The first and second trench areas are dimensioned so that a first charge storage capacity is equal to or greater than a second charge storage capacity. A tapped CCD shift register includes a first CCD shift register segment and a second shift register segment, both the first and second CCD shift register segments being characterized by a pitch length in the longitudinal direction. The first CCD shift register segment includes a sense node, and the second CCD shift register segment includes a beginning shift register charge storage element, both the sense node and the beginning shift register charge storage element being disposed within one pitch length in the longitudinal direction.

Method of making CCD readout register having multiple outputs

A structure for a charge coupled device (CCD) to minimize effects of masking defects of a predetermined dimensional extent includes a plurality of sets of conductors, a plurality of strapping networks and a connection matrix of via contacts. Each set of the plurality of sets of conductors includes a plurality of parallel elongate first conductors oriented in a first direction and disposed substantially in a first plane, each first conductor being comprised of a first material and characterized by a first sheet resistance per square of conductor. Each network of the plurality of strapping networks includes a plurality of parallel elongate second conductors oriented in a second direction transverse to the first direction and being disposed substantially in a second plane insulatively spaced apart from the first plane, each second conductor being comprised of a second material and characterized by a second sheet resistance per square of conductor, the second sheet resistance being less than the first sheet resistance. Each via contact of the connection matrix of via contacts connects a conductor of the plurality of first conductors of one of the sets of conductors with a conductor of the plurality of second conductors of one of the strapping networks, the connection matrix having a first via contact. Distances between the first via contact and each other via contact of the connection matrix are greater than the predetermined dimensional extent while a first lateral spacing between adjacent conductors of the plurality of first conductors is less than the predetermined dimensional extent, and while a second lateral spacing between adjacent conductors of the plurality of second conductors is less than the predetermined dimensional extent.

Integrated circuit defect tolerant architecture

A CCD shift register includes a first gate electrode, a second gate electrode disposed adjacent to and longitudinally spaced from the first gate electrode, and a buried layer having a first dopant impurity concentration. The first gate electrode is disposed over the buried layer so as to define a first buried layer area. The second gate electrode is disposed over the buried layer so as to define a second buried layer area greater than the first buried layer area. In the buried layer, a trench region is formed so as to have a second dopant impurity concentration greater than the first dopant impurity concentration. The first gate electrode is disposed over the trench region so as to define a first trench area. The second gate electrode being disposed over the trench region so as to define a second trench area less than the first trench area. In the CCD shift register, the first buried layer area defines an area for a first charge storage element characterized by a first charge storage capacity, the first charge storage capacity being a function of the first trench area. The second buried layer area defines an area for a second charge storage element characterized by a second charge storage capacity, the second charge storage capacity being a function of the second trench area. The first and second trench areas are dimensioned so that the first charge storage capacity is equal to or greater than the second charge storage capacity. A tapped CCD shift register includes a first CCD shift register segment and a second shift register segment, both the first and second CCD shift register segments being characterized by a pitch length in the longitudinal direction. The first CCD shift register segment includes a sense node, and the second CCD shift register segment includes a beginning shift register charge storage element, both the sense node and the beginning shift register charge storage element being disposed within one pitch length in the longitudinal direction.

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Boyne City, MI, United States of America

Michael George Farrier