Nxp Usa, Inc.

Freescale Semiconductor,inc.

Michael Garrett Neaves

Jon Scott Choy

Michael Alan Sadd

Perry H Pelley

Ravindraraj Ramaraju

A memory includes a global reference circuit for generating a signal that controls the resistance of a plurality of reference devices used to read data in memory cells by sense amplifiers of the memory. The signal is generated by an output of an operational amplifier of the global reference circuit. The operational amplifier includes a first input whose voltage is set by flowing current through a reference circuit and a second input whose voltage is set by flowing current through a master reference device. The signal controls the resistance of the master reference device such that the voltages of the inputs of the operational amplifier match.

Memory with a global reference circuit

A charge pump comprises one or more pump stages for providing a negative boosted output voltage. Each of the one or more pump stages comprises a P-channel transistor formed in an isolated P-well and an N-channel transistor coupled in series with the P-channel transistor. Forming the P-channel transistor in the isolated P-well essentially eliminates a raised threshold voltage due to body effect.

Charge pump circuit for providing multiplied voltage

In one embodiment, a sense amplifier circuit includes two current paths. Each path includes a transistor configured as a current source during a memory read operation and a second transistor. During the first phase of a memory read operation, the first current path is coupled to one cell and the second current path is coupled to a second cell. The sense amplifier circuit includes a capacitor that during a first phase of a memory read operation, is coupled between two corresponding nodes of the two paths to store a voltage difference between the two nodes. During the second phase, the cell/current path couplings are swapped and the capacitor is coupled to the control terminal of one of the second transistors to control the conductivity of the transistor for adjusting a voltage of an output node to indicate the value of the data being read.

Sense amplifier circuit

A sense amplifier circuit includes a sampling capacitor coupled to the input of an inverting amplifier. The output of the inverting amplifier is coupled to a transistor that includes a current terminal. The memory read operation includes two phases. During a first phase, a terminal of the capacitor is coupled to a first cell. During a second phase, the terminal of the capacitor is coupled a second cell.

A charge pump system includes a comparator having a first input coupled to a first reference voltage, a second input coupled to a feedback signal and an output coupled to control operation of a voltage controlled oscillator. The feedback signal is coupled to an output of the charge pump system. An amplifier has a first input coupled to a second reference voltage, a second input coupled to the feedback signal, and an output coupled as input to the voltage controlled oscillator. A gain of the amplifier is lower than a gain of the comparator.

Voltage generator with ramp rate control

A charge pump system includes a charge pump, a switchable impedance, a comparator, and a capacitor. The switchable impedance has an input coupled to the output of the charge pump. The comparator has a first input coupled to the output of the switchable impedance, a second input coupled to a reference, and an output coupled to the input of the charge pump. The capacitor has a first terminal coupled to the output of the charge pump and a second terminal coupled to the first input of the comparator. The switchable impedance causes a first impedance between the first and second terminals of the capacitor during a start-up operation of the charge pump system and a second impedance between the first and second terminals of the capacitor during a steady-state operation of the charge pump system, wherein the first impedance is lower than the second impedance.

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Austin, TX, United States of America

Michael Garrett Neaves