Pixelworks, Inc.

Infocus Corporation

Infocus Systems, Inc.

Other

Michael G West

Robert Y Greenberg

Jamie J LeVasseur

Jeffrey Alan Gohman

Alan L Zimmerman

A system and method for converting a pixel rate of a digital image frame is provided. The system includes a display controller with an embedded buffer and programmable input and output buffers. The input buffer writes lines of the frame at a source pixel rate while the output pointer reads out lines of the frame at a display pixel rate thereby allowing display of an image having a source pixel rate that is different, e.g., higher, than a display pixel rate.

Systems and methods for converting a pixel rate of an incoming digital image frame

System and method for converting a pixel rate of an incoming digital image frame

A methodAn apparatus and systemfor producing a digital video signal from an analog video signal, the analog video signal including an analog video data signal that is raster scanned in lines across a CRT screen to form consecutive frames of video information, the raster scanning controlled by use of a horizontal synchronizing signal(H)()that controls a line scan rate, and a vertical synchronizing signal(V)()that controls a frame refresh rate, to produce consecutive frames of video information, wherein the digital signal is produced by generating a pixel clock signal with pixel clocks for repetitively sampling instantaneous values of the analog video data signal, and digitizing the analog video data signal based on the pixel clock sampling. An expected width E, measured in number of pixel clocks, of a video image producible by the analog video signal is estimated, and an actual width W, measured in number of pixel clocks, of the video image producible by the analog video signal is calculated. The actual width W is compared with the expected width E. When E does not equal W, at least one of a frequency component and a phase component of the pixel clock signal is adjusted until E equals W.

Method and apparatus for automatic pixel clock phase and frequency correction in analog to digital video signal conversion

A system including a failsafe mechanism adapted to visually display frame locked digital image data and a method therefor. The system receives input image data at an input frame rate and/or input resolution. The packing circuit generates coded image data by compressing the input image data. An unpacking circuit decompresses the coded image and provides output image data to a display device at an output frame rate and/or output resolution.

Failsafe display of frame locked graphics

A system and method is provided for aligning multi-channel coded data over multiple clock periods. Data is received through a plurality of data channels and stored in a plurality of latches or queues. Data is scanned to determine whether a valid data transition has occurred. Once a valid transition is detected on all of the plurality of data channels, data is substantially simultaneously read out of the latches or queues resulting in synchronized or aligned data being provided at the output.

System and method for aligning multi-channel coded data over multiple clock periods

The image scaling memory system of the present invention eliminates the use of internal or external line memories by using an existing frame memory coupled with an input buffer and a plurality of output buffers for providing a vertical scalar with simultaneous parallel access to multiple lines of data. Additionally, the image scaling memory system of the present invention, including the frame memory, is embedded into an integrated circuit. Thus, the image scaling circuit of the present invention improves reliability, lowers cost, and improves silicon area usage. The frame memory is coupled to an input buffer at an input side and a plurality of output buffers at an output side. The plurality of output buffers is positioned between the frame memory and the vertical scalar. Each output buffer sequentially gains access to and transfers portions of image lines from the frame buffer. Each output buffer stores only a portion of an image line resulting in relatively small output buffers. The plurality of output buffers provides the vertical scalar with simultaneous parallel access to multiple lines of buffered digital image data. The frame memory preferably comprises DRAM that stores the image data such that row faults are minimized. The DRAM frame memory preferably includes at least two memory banks, each including a plurality of rows and a plurality of columns. The DRAM frame memory has multiple purposes including storing digital image data frames for sample rate conversion, as well as, storing bitmaps for access by an On Screen Display controller and storing microprocessor data for access by a microprocessor.

Ultra-high bandwidth multi-port memory system for image scaling applications

A method for producing a digital video signal from an analog video signal, the analog video signal including an analog video data signal that is raster scanned in lines across a CRT screen to form consecutive frames of video information, the raster scanning controlled by use of a horizontal synchronizing signal (H ) that controls a line scan rate, and a vertical synchronizing signal (V ) that controls a frame refresh rate, to produce consecutive frames of video information, wherein the digital video signal is produced by generating a pixel clock signal with pixel clocks for repetitively sampling instantaneous values of the analog video data signal, and digitizing the analog video data signal based on the pixel clock sampling. An expected width E, measured in number of pixel clocks, of a video image producible by the analog video signal is estimated, and an actual width W, measured in number of pixel clocks, of the video image producible by the analog video signal is calculated. The actual width W is compared with the expected width E. When E does not equal W, at least one of a frequency component and a phase component of the pixel clock signal is adjusted unit E equals W.

An image scaling circuit for increasing or decreasing the size of a sampled image to match a fixed resolution display. The circuit includes means for resizing the image in the horizontal and vertical dimension using independent sample rate converters. The sample rate converters increase or decrease the image size by a factor of Lx/Mx in the horizontal dimension and Ly/My in the vertical dimension where Lx and Ly are integers and Mx and My are decimal numbers of arbitrary precision to provide fine scaling control. In addition, image warping is conveniently implemented by varying the down sample ratios Mx and My on a pixel by pixel and/or line by line basis.

Image scaling circuit for fixed pixed resolution display

An image projector is provided with a light source and a light valve positioned downstream of the light source. An optical path is defined between the light source and the light valve. To accommodate various image viewing formats, a plurality of optical integrators is positioned between the light source and the light valve. Each of the plurality of optical integrators is movable laterally of the optical path and is positionable in the optical path. Light from the light source is transmitted to the light valve through the particular optical integrator positioned in the optical path. Each optical integrator is constructed to produce a unique display format for the light transmitted therethrough to the light valve, in order the accommodate different display formats such as standard and letter-box without wasting light.

Image projection system with variable display format

A method for producing a digital video signal from an analog video signal, the analog video signal including an analog video data signal that is raster scanned in lines across a CRT screen to form consecutive frames of video information, the raster scanning controlled by use of a horizontal synchronizing signal (H.sub.snyc) that controls a line scan rate, and a vertical synchronizing signal (V.sub.snyc) that controls a frame refresh rate, to produce consecutive frames of video information, wherein the digital video signal is produced by generating a pixel clock signal with pixel clocks for repetitively sampling instantaneous values of the analog video data signal, and digitizing the analog video data signal based on the pixel clock sampling. An expected width E, measured in number of pixel clocks, of a video image producible by the analog video signal is estimated, and an actual width W, measured in number of pixel clocks, of the video image producible by the analog video signal is calculated. The actual width W is compared with the expected width E. When E does not equal W, at least one of a frequency component and a phase component of the pixel clock signal is adjusted until E equals W.

Method and apparatus for automatic pixel clock phase and frequency

A method for producing a digital video signal from an analog video signal, the analog video signal including an analog video data signal that is raster scanned in lines across a CRT screen to form consecutive frames of video information, the raster scanning controlled by use of a horizontal synchronizing signal (H.sub.sync) that controls a line scan rate, and a vertical synchronizing signal (V.sub.sync) that controls a frame refresh rate, to produce consecutive frames of video information, wherein the digital video signal is produced by generating a pixel clock signal with pixel clocks for repetitively sampling instantaneous values of the analog video data signal, and digitizing the analog video data signal based on the pixel clock sampling. An expected width E, measured in number of pixel clocks, of a video image producible by the analog video signal is estimated, and an actual width W, measured in number of pixel clocks, of the video image producible by the analog video signal is calculated. The actual width W is compared with the expected width E. When E does not equal W, at least one of a frequency component and a phase component of the pixel clock signal is adjusted until E equals W. The phase of the pixel clock signal may also be corrected by selecting a selected pixel component, and iteratively adjusting the pixel clock phase until a jitter zone of a pixel clock pulse is centrally registered with the selected pixel component.

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Portland, OR, United States of America

Michael G West