Analog Devices,inc.

Michael G Tuthill

Dennis A Dempsey

David J Clarke

Michael F Keaveney

Denis Ellis

William Hunt

Evaldo M Miranda, Jr

Brian Anthony Moane

Michael P Daly

Kieran K Heffernan

John Blake

Paschal Thomas Minogue

Denis J Doyle

Martin Gerard Cotter

Liam Joseph White

Keith A Moloney

A phase detection apparatus is described for use in a phase lock loop (PLL). The apparatus has a first input for a reference signal, a second input for a loop feedback signal and an output for the phase difference signal. Two D-type flips flops are provided, the first being clocked with the reference signal and the second with the loop feedback signal. The output of the second flip-flop is delayed relative to the first flip-flop, thereby effecting minimal overlap, when using the phase detection apparatus in a fractional- N phase lock loop, of the interpolator activity with that of the charge pump.

Phase frequency detector with adjustable offset

An input protection device is provided for protecting a circuit structure which is coupled to a first node, the device comprising a first lightly-doped region of P-type material with a lightly doped well of N-type material formed in it. Two regions of heavily doped N-type and P-type material, which are electrically connected to the first node, are formed in the well of N-type material. A third heavily doped region of N type material is formed in the first lightly-doped region of P-type material and is electrically connected to a reference node. In a first aspect of this invention, the third heavily doped region of N type material is formed in a second well of N-type material, which in turn is formed in the first lightly-doped region of P-type material. In this first aspect of the invention a further region of heavily doped P-type material is formed in the second well of N-type material, this further region of heavily doped P-type material being electrically connected to the reference node. In a second aspect to the invention, a further region of heavily doped P-type material is formed in the first lightly-doped region of P-type material. In a third aspect to the invention, the third heavily doped region of N type material is formed in a second well of N-type material, which in turn is formed in the first lightly-doped region of P-type material. In this third aspect of the invention a further region of heavily doped P-type material is formed in the second well of N-type material, this further region of heavily doped P-type material being electrically connected to the reference node, with a further region of heavily doped P-type material formed in the first lightly-doped region of P-type material. Accordingly, an input protection device for protecting pins of an integrated circuit is described having both bipolar and unipolar characteristics. The input protection device may be constructed as a discrete device or as part of an integrated circuit and provides for breakdown voltages in excess of a supply voltage to an integrated circuit. The characteristics, in particular the breakdown voltage, of the input protection device are alterable by adjusting its layout, in contrast to a known method of altering such characteristics by altering doping levels.

SCR cell for electrical overstress protection of electronic circuits

A decoupled switched current temperature circuit with compounded .DELTA.V.sub.be includes an amplifier having an inverting input with corresponding non-inverting output and a non-inverting input with a corresponding inverting output; a PN junction connected to the non-inverting input through a first input capacitor and a voltage reference circuit is connected to the inverting input through a second input capacitor; a current supply includes a low current source and a high current source; a switching device applies the high current source to the PN junction and applies the low current source to the PN junction for providing the .DELTA.V.sub.be of the PN junction to the first capacitor; a first feedback capacitor is interconnected between the inverting output and the non-inverting input and a second feedback capacitor is interconnected between the non-inverting output and inverting input of the amplifier to define the gain on each of the inputs to produce a differential voltage across the outputs representative of the temperature of the PN junction; first and second reset switching devices discharge the first and second feedback capacitors, respectively, and a multi-phase switched device alternately interchanges the connection of the first and second input capacitors with the amplifier inputs for compounding the single .DELTA.V.sub.be .

Decoupled switched current temperature circuit with compounded .DELTA.V

A switched current temperature sensor circuit with compounded .DELTA.V.sub.BE includes an amplifier having an inverting input with a corresponding non-inverting output, and a non-inverting input with a corresponding inverting output; a first PN junction connected to the non-inverting input through a first input capacitor and a second PN junction connected to the inverting input through a second input capacitor; a current supply including a low current source and a high current source; a switching device for applying in the auto zero mode the high current source to a first terminal of the first PN junction and the low current source to a first terminal of the second PN junction for providing the V.sub.BE1 of the first junction to the first capacitor and for providing the V.sub.BE2 of the second junction to the second capacitor and for applying in the temperature measurement mode the low current source to the first terminal of the first PN junction and the high current source to the first terminal of the second PN junction for providing the negative .DELTA.V.sub.BE1 of the first PN junction to the first capacitor and the positive .DELTA.V.sub.BE2 of the second PN junction to the second capacitor. The first feedback capacitor interconnected between the inverting output and non-inverting input and a second feedback capacitor interconnected between the non-inverting output and inverting input in the amplifier to define the gain on each of the .DELTA.V.sub.BE inputs to produce a differential voltage across the outputs representative of the average temperature of the PN junctions; and first and second reset switching devices for discharging the first and second feedback capacitors, respectively, and for enabling the amplifier to equalize its input in the auto-zero mode.

Switched current temperature sensor circuit with compounded

A switching bandgap reference circuit with compounded .DELTA.V.sub.BE includes an amplifier having an output, an inverting input and a non-inverting input; a first PN junction connected to the non-inverting input; a second PN junction connected to the inverting input through an input capacitor; a low current source and a high current source; a switching device for applying in the auto zero mode the low current source to a first terminal of the first PN junction and the high current source to a first terminal of the second PN junction for establishing the V.sub.BE, of the first junction at both the inputs of the amplifier and for applying in the valid reference mode the high current source to the first terminal of the first PN junction and the low current source to the first terminal of the second PN junction for establishing the positive .DELTA.V.sub.BE, of the first PN junction to both the inputs of the amplifier and applying the negative .DELTA.V.sub.BE2 of the second PN junction to the input capacitor to produce a voltage of .DELTA.V.sub.BE1 plus (-.DELTA.V.sub.BE2) across the input capacitor; a feedback capacitor connected between the output and inverting input of the amplifier to define the gain on the combined .DELTA.V.sub.BE voltages to produce a temperature stabilized voltage at the output of the amplifier and a reset switching device for discharging the feedback capacitor and enabling the amplifier to equalize its inputs in the auto zero mode.

Switching bandgap reference circuit with compounded

A switch architecture for a digital-to-analog converter provides improved linearity. A first switch for one leg of the R/2R resistance ladder includes a unit resistor coupled between the MOSFET devices of the switch and the respective leg of the R/2R ladder. The on resistances of the MOSFET devices of the first switch are controlled in response to a reference value, such as the resistance of a reference resistor, which may have a resistance and other characteristics similar to the unit resistor. Other switches for other legs of the R/2R ladder also have a unit resistor, or other MOSFET devices having an on resistance controlled in relation to the reference value. Additional switches for other legs of the R/2R ladder may also have MOSFET devices of varying width to channel (W/L) ratios. Each of these approaches may be combined to achieve a binary weighting or an alternate weighting between legs of the R/2R ladder, in order to provide low linearity error.

Switch architecture for R/2R digital to analog converters

A digital-to-analog converter comprising a set of identical DAC cells each including: (1) a PNP bipolar current source transistor producing a continuous output current (equal values for all DAC cells), (2) a pair of PMOS switches connected to the collector of the bipolar transistor to divert the output current to either a ground line or a corresponding node of an R/2R ladder, (3) ladder circuitry for maintaining the full-scale ladder voltage below a predetermined level which keeps the PMOS switches in the saturated region of their characteristics, and (4) make-before-break switch control circuitry to close the PMOS switch being activated prior to opening the other PMOS switch.

High-speed digital-to-analog converter with BiMOS cell structure

A CMOS D/A converter for use in a voltage-mode and having complementary-driven switch pairs for V.sub.ref and A.sub.gnd respectively. The 'ON' gate voltage of the A.sub.gnd switch is adjusted in accordance with the value of V.sub.ref, to give switch V.sub.GS equality and therefore 'ON' resistance matching with the V.sub.ref switch over a wide range of reference voltage. Circuits are shown for developing the A.sub.gnd gate voltage varying with V.sub.ref.

Extended reference range, voltage-mode CMOS D/A converter

A digital-to-analog converter capable of high resolution performance, e.g. for converting 16-bit digital signals, comprising a cascaded two-stage device wherein the first stage consists of a segment converter with a series-connected string of resistors and switches operable by a set of high-order input bits for selecting the voltage across any one of the resistors, buffer amplifiers for directing the selected voltage to the input of a second-stage converter comprising a CMOS DAC with an R/2R ladder controlled by a set of lower order bits to interpolate between the limits of the selected voltage from the first stage, and wherein the switches for the first stage function to interchange the roles of the buffer amplifiers for each step up (or down) the resistor string so as to eliminate or minimize differential non-linearity errors due to offset mismatch between the buffer amplifiers.

High resolution digital-to-analog converter

A digital-to-analog converter capable of high resolution performance, e.g. for converting 16-bit digital signals, comprising a cascaded two-stage device wherein the first stage consists of a segment converter with a series-connected string of resistors and switches operable by a set of higher-order input bits for selecting the voltage across any one of the resistors, buffer amplifiers for directing the selected voltage to the input of a second-stage converter comprising a CMOS DAC with an R/2R ladder controlled by a set of lower order bits to interpolate between the limits of the selected voltage from the first stage, and wherein the switches for the first stage function to interchange the roles of the buffer amplifiers for each step up (or down) the resistor string so as to eliminate or minimize differential non-linearity errors due to offset mismatch between the buffer amplifiers.

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Limerick, Ireland

Michael G Tuthill