Advanced Micro Devices Corporation

Globalfoundries Inc.

Other

Hewlett-packard Development Company, L.p.

Michael G McIntyre

Richard W Jarvis

Michael Alan Retersdorf

Kevin R Lensing

Charlie Reading

Paul J Steffan

Michael Sean McGee

John Lee Nistler

Iraj Emami

Steven P Reeves

James Randall Walker

Alex Bierwag

Alfredo V Herrera

Andrew Drozda-Freeman

Thinh Ngo

Vijay Sankaran

Zhuqing Zong

James E Morris

A method, apparatus, and a system for generating a binary mapping of wafer regions using measured value. A first measured value relating to processing a first workpiece is acquired. A second measured value relating to a second workpiece is acquired. At least a first region common to the first and second workpieces is defined. A determination is made as to whether the results associated with the first or second measured value is above a predetermined threshold. A first binary value is assigned to the first region based upon a determination that the results associated the first or second measured value data is above the threshold.

Method and apparatus for analysis of continuous data using binary parsing

A method includes receiving a first set of parameters associated with a subset of a plurality of die on a wafer. A die health metric is determined for at least a portion of the plurality of die based on the first set of parameters. The die health metric includes at least one process component associated with the fabrication of the die and at least one performance component associated with an electrical performance characteristic of the die. At least one of the die is tested. A protocol of the testing is determined based on the associated die health metric.

Determining die test protocols based on process health

A method includes defining a hierarchy of test routines in a test program for testing integrated circuit devices. A first device is tested at a first screening level in the hierarchy. The first device is tested at a second detailed level in the hierarchy responsive to the first device failing the testing at the first screening level.

Method and apparatus for implementing scaled device tests

A method includes loading a plurality of integrated circuit devices into a tester. At least one parameter is determined for each of the integrated circuit devices using the tester. At least one relative acceptance criterion associated with the parameter is determined based on the determined parameters for the plurality of integrated circuit devices. A pass/fail status of each of the integrated circuit devices is determined using the relative acceptance criterion.

Method and apparatus for relative testing of integrated circuit devices

A method, apparatus, and a system for generating an index for storing data. A pattern associated with a first set of data is determined. The first set of data is stored. A determination is made as to whether the pattern associated with a second set of data corresponds to the pattern associated with the first set of data. An index associated with the first set of data is correlated to the second set of data in response to determining that the pattern associated with the second set of data corresponds to the pattern associated with the first set of data.

Method and apparatus for manufacturing data indexing

A method includes receiving a metrology report including metrology data collected by a metrology tool, position data associated with the metrology data, and context data associated with the metrology tool. A first coordinate system employed by the metrology tool is determined based on the context data. The position data is transformed from the first coordinate system to a second coordinate system to generate transformed position data. The transformed position data is associated with the metrology data.

Method and apparatus for implementing a universal coordinate system for metrology data

A method for converting data includes generating a first data vector of data measurements related to processing of at least one workpiece. Each element of the first data vector is associated with at least one of a plurality of positions on the workpiece. A cumulative distribution of the elements in the first data vector is generated. An outlier region of the data measurements is identified based on the cumulative distribution. A binary outlier data vector is generated from the first data vector by assigning a first binary value to the data elements in the first data vector in the outlier region and assigning a second binary value to the remaining data elements in the first data vector.

Method and apparatus for identifying outlier data

A method, apparatus, and a system for providing data representation associated with non-sampled workpieces. Measured metrology data relating to a first workpiece is received. Metrology data corresponding to a second workpiece is approximated based upon the metrology data relating to the first workpiece to provide a projected metrology data relating to the second workpiece.

Data representation relating to a non-sampled workpiece

A front-end-of-line piece of a semiconductor die is manufactured in a first manufacturing line. A back-end-of-line piece of a semiconductor die is manufactured using a second manufacturing line, which will typically be different than the first manufacturing line. The front-end-of-line piece and the back-end-of-line piece are combined during a joining process to form a semiconductor die. The semiconductor die is subsequently tested to determine if the semiconductor die is a functional semiconductor die.

Split manufacturing method for advanced semiconductor circuits

A method and apparatus for analyzing patterns in semiconductor wafers wherein the patterns are compared to a plurality of patterns stored in a common pattern library. A spatial pattern recognition engine is operable to receive a first set of data corresponding to a pattern on a semiconductor wafer and to generate a normalized contour representation of said first data set. A pattern analyzer compares the normalized data set to a plurality of reference contour data sets stored in a common pattern data reference library and generates a correlation label associating the first data set with one of the plurality of reference contour data sets. The label associated with the first data set is stored in a label storage database that can be accessed to perform subsequent analysis on the data associated with a specific wafer. The system can be used to analyze multiple types of patterns, including defect data, bin data, positional parameter data and in-line site data.

Universal spatial pattern recognition system

A portable device includes a location detector, a time detector, and an alarm module to generate alarms based on both time-based and location-based criteria. A current time provided by the time detector is compared to a time-based criterion, and a current geographical location provided by the location detector (e.g., global positioning system or GPS receiver) is compared to a location-based criterion to determine whether or not to generate an alarm.

Generating an alarm based on location and time

A test structure which includes a first conductive feature layer and a second conductive feature layer is described. The first conductive feature layer includes a first conductive line. The second conductive feature layer includes a second conductive line. A daisy chain conductive feature is also included in the test structure. The daisy chain conductive feature includes portions on the first and second conductive feature layers which are interconnected to each other by vias.

Integrated defect monitor structures for conductive features on a semiconductor topography and method of use

A test structure which includes alternating grounded and floating conductive lines may be used to test the formation of conductive features on an integrated circuit topography. During irradiation of the conductive lines from an electron source, the grounded conductive lines will appear darker than the floating conductive lines when the test structure is inspected. If a short occurs between the conductive lines, due to an extra material defect, the portion of the floating line in the vicinity of the defect will also appear darkened. If an open appears along a grounded line, the non-grounded portion of the grounded line will be glowing. The grounded conductive lines are preferably grounded through a depletion-mode transistor. By applying a voltage to the transistor, the grounded line may be disconnected from ground, allowing electrical testing of the test structure. The electrical testing may be used to validate the voltage contrast methodology, as well as determine the approximate size of defects formed on the test structure.

Multipurpose defect test structure with switchable voltage contrast capability and method of use

A method of identifying individual semiconductor devices with a unique inscription during the manufacturing process for the semiconductor devices. Each individual semiconductor device is marked during a final lithographic stepping exposure with a direct write laser mounted either in the stepper in the lithographic system working concurrently with the stepping fields during the final metal layer lithographic stepping exposure or during a post stepping pre-development treatment. The marking on the devices includes device identification, lot number and die number.

Growing community of inventors

Austin, TX, United States of America

Michael G McIntyre